0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2016 MediaTek Inc.
0004 * Author: Mars.C <mars.cheng@mediatek.com>
0005 */
0006
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009
0010 / {
0011 compatible = "mediatek,mt6755";
0012 interrupt-parent = <&sysirq>;
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 psci {
0017 compatible = "arm,psci-0.2";
0018 method = "smc";
0019 };
0020
0021 cpus {
0022 #address-cells = <1>;
0023 #size-cells = <0>;
0024
0025 cpu0: cpu@0 {
0026 device_type = "cpu";
0027 compatible = "arm,cortex-a53";
0028 enable-method = "psci";
0029 reg = <0x000>;
0030 };
0031
0032 cpu1: cpu@1 {
0033 device_type = "cpu";
0034 compatible = "arm,cortex-a53";
0035 enable-method = "psci";
0036 reg = <0x001>;
0037 };
0038
0039 cpu2: cpu@2 {
0040 device_type = "cpu";
0041 compatible = "arm,cortex-a53";
0042 enable-method = "psci";
0043 reg = <0x002>;
0044 };
0045
0046 cpu3: cpu@3 {
0047 device_type = "cpu";
0048 compatible = "arm,cortex-a53";
0049 enable-method = "psci";
0050 reg = <0x003>;
0051 };
0052
0053 cpu4: cpu@100 {
0054 device_type = "cpu";
0055 compatible = "arm,cortex-a53";
0056 enable-method = "psci";
0057 reg = <0x100>;
0058 };
0059
0060 cpu5: cpu@101 {
0061 device_type = "cpu";
0062 compatible = "arm,cortex-a53";
0063 enable-method = "psci";
0064 reg = <0x101>;
0065 };
0066
0067 cpu6: cpu@102 {
0068 device_type = "cpu";
0069 compatible = "arm,cortex-a53";
0070 enable-method = "psci";
0071 reg = <0x102>;
0072 };
0073
0074 cpu7: cpu@103 {
0075 device_type = "cpu";
0076 compatible = "arm,cortex-a53";
0077 enable-method = "psci";
0078 reg = <0x103>;
0079 };
0080 };
0081
0082 uart_clk: dummy26m {
0083 compatible = "fixed-clock";
0084 clock-frequency = <26000000>;
0085 #clock-cells = <0>;
0086 };
0087
0088 timer {
0089 compatible = "arm,armv8-timer";
0090 interrupt-parent = <&gic>;
0091 interrupts = <GIC_PPI 13
0092 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0093 <GIC_PPI 14
0094 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0095 <GIC_PPI 11
0096 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0097 <GIC_PPI 10
0098 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0099 };
0100
0101 sysirq: intpol-controller@10200620 {
0102 compatible = "mediatek,mt6755-sysirq",
0103 "mediatek,mt6577-sysirq";
0104 interrupt-controller;
0105 #interrupt-cells = <3>;
0106 interrupt-parent = <&gic>;
0107 reg = <0 0x10200620 0 0x20>;
0108 };
0109
0110 gic: interrupt-controller@10231000 {
0111 compatible = "arm,gic-400";
0112 #interrupt-cells = <3>;
0113 interrupt-parent = <&gic>;
0114 interrupt-controller;
0115 reg = <0 0x10231000 0 0x1000>,
0116 <0 0x10232000 0 0x2000>,
0117 <0 0x10234000 0 0x2000>,
0118 <0 0x10236000 0 0x2000>;
0119 };
0120
0121 uart0: serial@11002000 {
0122 compatible = "mediatek,mt6755-uart",
0123 "mediatek,mt6577-uart";
0124 reg = <0 0x11002000 0 0x400>;
0125 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
0126 clocks = <&uart_clk>;
0127 status = "disabled";
0128 };
0129
0130 uart1: serial@11003000 {
0131 compatible = "mediatek,mt6755-uart",
0132 "mediatek,mt6577-uart";
0133 reg = <0 0x11003000 0 0x400>;
0134 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
0135 clocks = <&uart_clk>;
0136 status = "disabled";
0137 };
0138 };
