0001 /*
0002 * Copyright (c) 2017 MediaTek Inc.
0003 * Author: YT Shen <yt.shen@mediatek.com>
0004 *
0005 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
0006 */
0007
0008 #include <dt-bindings/clock/mt2712-clk.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/memory/mt2712-larb-port.h>
0012 #include <dt-bindings/phy/phy.h>
0013 #include <dt-bindings/power/mt2712-power.h>
0014 #include "mt2712-pinfunc.h"
0015
0016 / {
0017 compatible = "mediatek,mt2712";
0018 interrupt-parent = <&sysirq>;
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021
0022 cluster0_opp: opp-table-0 {
0023 compatible = "operating-points-v2";
0024 opp-shared;
0025 opp00 {
0026 opp-hz = /bits/ 64 <598000000>;
0027 opp-microvolt = <1000000>;
0028 };
0029 opp01 {
0030 opp-hz = /bits/ 64 <702000000>;
0031 opp-microvolt = <1000000>;
0032 };
0033 opp02 {
0034 opp-hz = /bits/ 64 <793000000>;
0035 opp-microvolt = <1000000>;
0036 };
0037 };
0038
0039 cluster1_opp: opp-table-1 {
0040 compatible = "operating-points-v2";
0041 opp-shared;
0042 opp00 {
0043 opp-hz = /bits/ 64 <598000000>;
0044 opp-microvolt = <1000000>;
0045 };
0046 opp01 {
0047 opp-hz = /bits/ 64 <702000000>;
0048 opp-microvolt = <1000000>;
0049 };
0050 opp02 {
0051 opp-hz = /bits/ 64 <793000000>;
0052 opp-microvolt = <1000000>;
0053 };
0054 opp03 {
0055 opp-hz = /bits/ 64 <897000000>;
0056 opp-microvolt = <1000000>;
0057 };
0058 opp04 {
0059 opp-hz = /bits/ 64 <1001000000>;
0060 opp-microvolt = <1000000>;
0061 };
0062 };
0063
0064 cpus {
0065 #address-cells = <1>;
0066 #size-cells = <0>;
0067
0068 cpu-map {
0069 cluster0 {
0070 core0 {
0071 cpu = <&cpu0>;
0072 };
0073 core1 {
0074 cpu = <&cpu1>;
0075 };
0076 };
0077
0078 cluster1 {
0079 core0 {
0080 cpu = <&cpu2>;
0081 };
0082 };
0083 };
0084
0085 cpu0: cpu@0 {
0086 device_type = "cpu";
0087 compatible = "arm,cortex-a35";
0088 reg = <0x000>;
0089 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
0090 <&topckgen CLK_TOP_F_MP0_PLL1>;
0091 clock-names = "cpu", "intermediate";
0092 proc-supply = <&cpus_fixed_vproc0>;
0093 operating-points-v2 = <&cluster0_opp>;
0094 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0095 };
0096
0097 cpu1: cpu@1 {
0098 device_type = "cpu";
0099 compatible = "arm,cortex-a35";
0100 reg = <0x001>;
0101 enable-method = "psci";
0102 clocks = <&mcucfg CLK_MCU_MP0_SEL>,
0103 <&topckgen CLK_TOP_F_MP0_PLL1>;
0104 clock-names = "cpu", "intermediate";
0105 proc-supply = <&cpus_fixed_vproc0>;
0106 operating-points-v2 = <&cluster0_opp>;
0107 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0108 };
0109
0110 cpu2: cpu@200 {
0111 device_type = "cpu";
0112 compatible = "arm,cortex-a72";
0113 reg = <0x200>;
0114 enable-method = "psci";
0115 clocks = <&mcucfg CLK_MCU_MP2_SEL>,
0116 <&topckgen CLK_TOP_F_BIG_PLL1>;
0117 clock-names = "cpu", "intermediate";
0118 proc-supply = <&cpus_fixed_vproc1>;
0119 operating-points-v2 = <&cluster1_opp>;
0120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
0121 };
0122
0123 idle-states {
0124 entry-method = "psci";
0125
0126 CPU_SLEEP_0: cpu-sleep-0 {
0127 compatible = "arm,idle-state";
0128 local-timer-stop;
0129 entry-latency-us = <100>;
0130 exit-latency-us = <80>;
0131 min-residency-us = <2000>;
0132 arm,psci-suspend-param = <0x0010000>;
0133 };
0134
0135 CLUSTER_SLEEP_0: cluster-sleep-0 {
0136 compatible = "arm,idle-state";
0137 local-timer-stop;
0138 entry-latency-us = <350>;
0139 exit-latency-us = <80>;
0140 min-residency-us = <3000>;
0141 arm,psci-suspend-param = <0x1010000>;
0142 };
0143 };
0144 };
0145
0146 psci {
0147 compatible = "arm,psci-0.2";
0148 method = "smc";
0149 };
0150
0151 baud_clk: dummy26m {
0152 compatible = "fixed-clock";
0153 clock-frequency = <26000000>;
0154 #clock-cells = <0>;
0155 };
0156
0157 sys_clk: dummyclk {
0158 compatible = "fixed-clock";
0159 clock-frequency = <26000000>;
0160 #clock-cells = <0>;
0161 };
0162
0163 clk26m: oscillator@0 {
0164 compatible = "fixed-clock";
0165 #clock-cells = <0>;
0166 clock-frequency = <26000000>;
0167 clock-output-names = "clk26m";
0168 };
0169
0170 clk32k: oscillator@1 {
0171 compatible = "fixed-clock";
0172 #clock-cells = <0>;
0173 clock-frequency = <32768>;
0174 clock-output-names = "clk32k";
0175 };
0176
0177 clkfpc: oscillator@2 {
0178 compatible = "fixed-clock";
0179 #clock-cells = <0>;
0180 clock-frequency = <50000000>;
0181 clock-output-names = "clkfpc";
0182 };
0183
0184 clkaud_ext_i_0: oscillator@3 {
0185 compatible = "fixed-clock";
0186 #clock-cells = <0>;
0187 clock-frequency = <6500000>;
0188 clock-output-names = "clkaud_ext_i_0";
0189 };
0190
0191 clkaud_ext_i_1: oscillator@4 {
0192 compatible = "fixed-clock";
0193 #clock-cells = <0>;
0194 clock-frequency = <196608000>;
0195 clock-output-names = "clkaud_ext_i_1";
0196 };
0197
0198 clkaud_ext_i_2: oscillator@5 {
0199 compatible = "fixed-clock";
0200 #clock-cells = <0>;
0201 clock-frequency = <180633600>;
0202 clock-output-names = "clkaud_ext_i_2";
0203 };
0204
0205 clki2si0_mck_i: oscillator@6 {
0206 compatible = "fixed-clock";
0207 #clock-cells = <0>;
0208 clock-frequency = <30000000>;
0209 clock-output-names = "clki2si0_mck_i";
0210 };
0211
0212 clki2si1_mck_i: oscillator@7 {
0213 compatible = "fixed-clock";
0214 #clock-cells = <0>;
0215 clock-frequency = <30000000>;
0216 clock-output-names = "clki2si1_mck_i";
0217 };
0218
0219 clki2si2_mck_i: oscillator@8 {
0220 compatible = "fixed-clock";
0221 #clock-cells = <0>;
0222 clock-frequency = <30000000>;
0223 clock-output-names = "clki2si2_mck_i";
0224 };
0225
0226 clktdmin_mclk_i: oscillator@9 {
0227 compatible = "fixed-clock";
0228 #clock-cells = <0>;
0229 clock-frequency = <30000000>;
0230 clock-output-names = "clktdmin_mclk_i";
0231 };
0232
0233 timer {
0234 compatible = "arm,armv8-timer";
0235 interrupt-parent = <&gic>;
0236 interrupts = <GIC_PPI 13
0237 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
0238 <GIC_PPI 14
0239 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
0240 <GIC_PPI 11
0241 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
0242 <GIC_PPI 10
0243 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
0244 };
0245
0246 topckgen: syscon@10000000 {
0247 compatible = "mediatek,mt2712-topckgen", "syscon";
0248 reg = <0 0x10000000 0 0x1000>;
0249 #clock-cells = <1>;
0250 };
0251
0252 infracfg: syscon@10001000 {
0253 compatible = "mediatek,mt2712-infracfg", "syscon";
0254 reg = <0 0x10001000 0 0x1000>;
0255 #clock-cells = <1>;
0256 };
0257
0258 pericfg: syscon@10003000 {
0259 compatible = "mediatek,mt2712-pericfg", "syscon";
0260 reg = <0 0x10003000 0 0x1000>;
0261 #clock-cells = <1>;
0262 };
0263
0264 syscfg_pctl_a: syscfg_pctl_a@10005000 {
0265 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
0266 reg = <0 0x10005000 0 0x1000>;
0267 };
0268
0269 pio: pinctrl@10005000 {
0270 compatible = "mediatek,mt2712-pinctrl";
0271 reg = <0 0x1000b000 0 0x1000>;
0272 mediatek,pctl-regmap = <&syscfg_pctl_a>;
0273 pins-are-numbered;
0274 gpio-controller;
0275 #gpio-cells = <2>;
0276 interrupt-controller;
0277 #interrupt-cells = <2>;
0278 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0279 };
0280
0281 scpsys: power-controller@10006000 {
0282 compatible = "mediatek,mt2712-scpsys", "syscon";
0283 #power-domain-cells = <1>;
0284 reg = <0 0x10006000 0 0x1000>;
0285 clocks = <&topckgen CLK_TOP_MM_SEL>,
0286 <&topckgen CLK_TOP_MFG_SEL>,
0287 <&topckgen CLK_TOP_VENC_SEL>,
0288 <&topckgen CLK_TOP_JPGDEC_SEL>,
0289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
0290 <&topckgen CLK_TOP_VDEC_SEL>;
0291 clock-names = "mm", "mfg", "venc",
0292 "jpgdec", "audio", "vdec";
0293 infracfg = <&infracfg>;
0294 };
0295
0296 uart5: serial@1000f000 {
0297 compatible = "mediatek,mt2712-uart",
0298 "mediatek,mt6577-uart";
0299 reg = <0 0x1000f000 0 0x400>;
0300 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
0301 clocks = <&baud_clk>, <&sys_clk>;
0302 clock-names = "baud", "bus";
0303 dmas = <&apdma 10
0304 &apdma 11>;
0305 dma-names = "tx", "rx";
0306 status = "disabled";
0307 };
0308
0309 rtc: rtc@10011000 {
0310 compatible = "mediatek,mt2712-rtc";
0311 reg = <0 0x10011000 0 0x1000>;
0312 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
0313 };
0314
0315 spis1: spi@10013000 {
0316 compatible = "mediatek,mt2712-spi-slave";
0317 reg = <0 0x10013000 0 0x100>;
0318 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
0319 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
0320 clock-names = "spi";
0321 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
0322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
0323 status = "disabled";
0324 };
0325
0326 iommu0: iommu@10205000 {
0327 compatible = "mediatek,mt2712-m4u";
0328 reg = <0 0x10205000 0 0x1000>;
0329 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
0330 clocks = <&infracfg CLK_INFRA_M4U>;
0331 clock-names = "bclk";
0332 mediatek,infracfg = <&infracfg>;
0333 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
0334 <&larb3>, <&larb6>;
0335 #iommu-cells = <1>;
0336 };
0337
0338 apmixedsys: syscon@10209000 {
0339 compatible = "mediatek,mt2712-apmixedsys", "syscon";
0340 reg = <0 0x10209000 0 0x1000>;
0341 #clock-cells = <1>;
0342 };
0343
0344 iommu1: iommu@1020a000 {
0345 compatible = "mediatek,mt2712-m4u";
0346 reg = <0 0x1020a000 0 0x1000>;
0347 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
0348 clocks = <&infracfg CLK_INFRA_M4U>;
0349 clock-names = "bclk";
0350 mediatek,infracfg = <&infracfg>;
0351 mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
0352 #iommu-cells = <1>;
0353 };
0354
0355 mcucfg: syscon@10220000 {
0356 compatible = "mediatek,mt2712-mcucfg", "syscon";
0357 reg = <0 0x10220000 0 0x1000>;
0358 #clock-cells = <1>;
0359 };
0360
0361 sysirq: interrupt-controller@10220a80 {
0362 compatible = "mediatek,mt2712-sysirq",
0363 "mediatek,mt6577-sysirq";
0364 interrupt-controller;
0365 #interrupt-cells = <3>;
0366 interrupt-parent = <&gic>;
0367 reg = <0 0x10220a80 0 0x40>;
0368 };
0369
0370 gic: interrupt-controller@10510000 {
0371 compatible = "arm,gic-400";
0372 #interrupt-cells = <3>;
0373 interrupt-parent = <&gic>;
0374 interrupt-controller;
0375 reg = <0 0x10510000 0 0x10000>,
0376 <0 0x10520000 0 0x20000>,
0377 <0 0x10540000 0 0x20000>,
0378 <0 0x10560000 0 0x20000>;
0379 interrupts = <GIC_PPI 9
0380 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
0381 };
0382
0383 apdma: dma-controller@11000400 {
0384 compatible = "mediatek,mt2712-uart-dma",
0385 "mediatek,mt6577-uart-dma";
0386 reg = <0 0x11000400 0 0x80>,
0387 <0 0x11000480 0 0x80>,
0388 <0 0x11000500 0 0x80>,
0389 <0 0x11000580 0 0x80>,
0390 <0 0x11000600 0 0x80>,
0391 <0 0x11000680 0 0x80>,
0392 <0 0x11000700 0 0x80>,
0393 <0 0x11000780 0 0x80>,
0394 <0 0x11000800 0 0x80>,
0395 <0 0x11000880 0 0x80>,
0396 <0 0x11000900 0 0x80>,
0397 <0 0x11000980 0 0x80>;
0398 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
0399 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
0400 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
0401 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
0402 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
0403 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
0404 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
0405 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
0406 <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
0407 <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
0408 <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
0409 <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
0410 dma-requests = <12>;
0411 clocks = <&pericfg CLK_PERI_AP_DMA>;
0412 clock-names = "apdma";
0413 #dma-cells = <1>;
0414 };
0415
0416 auxadc: adc@11001000 {
0417 compatible = "mediatek,mt2712-auxadc";
0418 reg = <0 0x11001000 0 0x1000>;
0419 clocks = <&pericfg CLK_PERI_AUXADC>;
0420 clock-names = "main";
0421 #io-channel-cells = <1>;
0422 status = "disabled";
0423 };
0424
0425 uart0: serial@11002000 {
0426 compatible = "mediatek,mt2712-uart",
0427 "mediatek,mt6577-uart";
0428 reg = <0 0x11002000 0 0x400>;
0429 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
0430 clocks = <&baud_clk>, <&sys_clk>;
0431 clock-names = "baud", "bus";
0432 dmas = <&apdma 0
0433 &apdma 1>;
0434 dma-names = "tx", "rx";
0435 status = "disabled";
0436 };
0437
0438 uart1: serial@11003000 {
0439 compatible = "mediatek,mt2712-uart",
0440 "mediatek,mt6577-uart";
0441 reg = <0 0x11003000 0 0x400>;
0442 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
0443 clocks = <&baud_clk>, <&sys_clk>;
0444 clock-names = "baud", "bus";
0445 dmas = <&apdma 2
0446 &apdma 3>;
0447 dma-names = "tx", "rx";
0448 status = "disabled";
0449 };
0450
0451 uart2: serial@11004000 {
0452 compatible = "mediatek,mt2712-uart",
0453 "mediatek,mt6577-uart";
0454 reg = <0 0x11004000 0 0x400>;
0455 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
0456 clocks = <&baud_clk>, <&sys_clk>;
0457 clock-names = "baud", "bus";
0458 dmas = <&apdma 4
0459 &apdma 5>;
0460 dma-names = "tx", "rx";
0461 status = "disabled";
0462 };
0463
0464 uart3: serial@11005000 {
0465 compatible = "mediatek,mt2712-uart",
0466 "mediatek,mt6577-uart";
0467 reg = <0 0x11005000 0 0x400>;
0468 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
0469 clocks = <&baud_clk>, <&sys_clk>;
0470 clock-names = "baud", "bus";
0471 dmas = <&apdma 6
0472 &apdma 7>;
0473 dma-names = "tx", "rx";
0474 status = "disabled";
0475 };
0476
0477 pwm: pwm@11006000 {
0478 compatible = "mediatek,mt2712-pwm";
0479 reg = <0 0x11006000 0 0x1000>;
0480 #pwm-cells = <2>;
0481 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
0482 clocks = <&topckgen CLK_TOP_PWM_SEL>,
0483 <&pericfg CLK_PERI_PWM>,
0484 <&pericfg CLK_PERI_PWM0>,
0485 <&pericfg CLK_PERI_PWM1>,
0486 <&pericfg CLK_PERI_PWM2>,
0487 <&pericfg CLK_PERI_PWM3>,
0488 <&pericfg CLK_PERI_PWM4>,
0489 <&pericfg CLK_PERI_PWM5>,
0490 <&pericfg CLK_PERI_PWM6>,
0491 <&pericfg CLK_PERI_PWM7>;
0492 clock-names = "top",
0493 "main",
0494 "pwm1",
0495 "pwm2",
0496 "pwm3",
0497 "pwm4",
0498 "pwm5",
0499 "pwm6",
0500 "pwm7",
0501 "pwm8";
0502 status = "disabled";
0503 };
0504
0505 i2c0: i2c@11007000 {
0506 compatible = "mediatek,mt2712-i2c";
0507 reg = <0 0x11007000 0 0x90>,
0508 <0 0x11000180 0 0x80>;
0509 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
0510 clock-div = <4>;
0511 clocks = <&pericfg CLK_PERI_I2C0>,
0512 <&pericfg CLK_PERI_AP_DMA>;
0513 clock-names = "main",
0514 "dma";
0515 #address-cells = <1>;
0516 #size-cells = <0>;
0517 status = "disabled";
0518 };
0519
0520 i2c1: i2c@11008000 {
0521 compatible = "mediatek,mt2712-i2c";
0522 reg = <0 0x11008000 0 0x90>,
0523 <0 0x11000200 0 0x80>;
0524 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
0525 clock-div = <4>;
0526 clocks = <&pericfg CLK_PERI_I2C1>,
0527 <&pericfg CLK_PERI_AP_DMA>;
0528 clock-names = "main",
0529 "dma";
0530 #address-cells = <1>;
0531 #size-cells = <0>;
0532 status = "disabled";
0533 };
0534
0535 i2c2: i2c@11009000 {
0536 compatible = "mediatek,mt2712-i2c";
0537 reg = <0 0x11009000 0 0x90>,
0538 <0 0x11000280 0 0x80>;
0539 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
0540 clock-div = <4>;
0541 clocks = <&pericfg CLK_PERI_I2C2>,
0542 <&pericfg CLK_PERI_AP_DMA>;
0543 clock-names = "main",
0544 "dma";
0545 #address-cells = <1>;
0546 #size-cells = <0>;
0547 status = "disabled";
0548 };
0549
0550 spi0: spi@1100a000 {
0551 compatible = "mediatek,mt2712-spi";
0552 #address-cells = <1>;
0553 #size-cells = <0>;
0554 reg = <0 0x1100a000 0 0x100>;
0555 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
0556 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
0557 <&topckgen CLK_TOP_SPI_SEL>,
0558 <&pericfg CLK_PERI_SPI0>;
0559 clock-names = "parent-clk", "sel-clk", "spi-clk";
0560 status = "disabled";
0561 };
0562
0563 nandc: nfi@1100e000 {
0564 compatible = "mediatek,mt2712-nfc";
0565 reg = <0 0x1100e000 0 0x1000>;
0566 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
0567 clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
0568 clock-names = "nfi_clk", "pad_clk";
0569 ecc-engine = <&bch>;
0570 #address-cells = <1>;
0571 #size-cells = <0>;
0572 status = "disabled";
0573 };
0574
0575 bch: ecc@1100f000 {
0576 compatible = "mediatek,mt2712-ecc";
0577 reg = <0 0x1100f000 0 0x1000>;
0578 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
0579 clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
0580 clock-names = "nfiecc_clk";
0581 status = "disabled";
0582 };
0583
0584 i2c3: i2c@11010000 {
0585 compatible = "mediatek,mt2712-i2c";
0586 reg = <0 0x11010000 0 0x90>,
0587 <0 0x11000300 0 0x80>;
0588 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
0589 clock-div = <4>;
0590 clocks = <&pericfg CLK_PERI_I2C3>,
0591 <&pericfg CLK_PERI_AP_DMA>;
0592 clock-names = "main",
0593 "dma";
0594 #address-cells = <1>;
0595 #size-cells = <0>;
0596 status = "disabled";
0597 };
0598
0599 i2c4: i2c@11011000 {
0600 compatible = "mediatek,mt2712-i2c";
0601 reg = <0 0x11011000 0 0x90>,
0602 <0 0x11000380 0 0x80>;
0603 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
0604 clock-div = <4>;
0605 clocks = <&pericfg CLK_PERI_I2C4>,
0606 <&pericfg CLK_PERI_AP_DMA>;
0607 clock-names = "main",
0608 "dma";
0609 #address-cells = <1>;
0610 #size-cells = <0>;
0611 status = "disabled";
0612 };
0613
0614 i2c5: i2c@11013000 {
0615 compatible = "mediatek,mt2712-i2c";
0616 reg = <0 0x11013000 0 0x90>,
0617 <0 0x11000100 0 0x80>;
0618 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
0619 clock-div = <4>;
0620 clocks = <&pericfg CLK_PERI_I2C5>,
0621 <&pericfg CLK_PERI_AP_DMA>;
0622 clock-names = "main",
0623 "dma";
0624 #address-cells = <1>;
0625 #size-cells = <0>;
0626 status = "disabled";
0627 };
0628
0629 spi2: spi@11015000 {
0630 compatible = "mediatek,mt2712-spi";
0631 #address-cells = <1>;
0632 #size-cells = <0>;
0633 reg = <0 0x11015000 0 0x100>;
0634 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>;
0635 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
0636 <&topckgen CLK_TOP_SPI_SEL>,
0637 <&pericfg CLK_PERI_SPI2>;
0638 clock-names = "parent-clk", "sel-clk", "spi-clk";
0639 status = "disabled";
0640 };
0641
0642 spi3: spi@11016000 {
0643 compatible = "mediatek,mt2712-spi";
0644 #address-cells = <1>;
0645 #size-cells = <0>;
0646 reg = <0 0x11016000 0 0x100>;
0647 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
0648 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
0649 <&topckgen CLK_TOP_SPI_SEL>,
0650 <&pericfg CLK_PERI_SPI3>;
0651 clock-names = "parent-clk", "sel-clk", "spi-clk";
0652 status = "disabled";
0653 };
0654
0655 spi4: spi@10012000 {
0656 compatible = "mediatek,mt2712-spi";
0657 #address-cells = <1>;
0658 #size-cells = <0>;
0659 reg = <0 0x10012000 0 0x100>;
0660 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>;
0661 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
0662 <&topckgen CLK_TOP_SPI_SEL>,
0663 <&infracfg CLK_INFRA_AO_SPI0>;
0664 clock-names = "parent-clk", "sel-clk", "spi-clk";
0665 status = "disabled";
0666 };
0667
0668 spi5: spi@11018000 {
0669 compatible = "mediatek,mt2712-spi";
0670 #address-cells = <1>;
0671 #size-cells = <0>;
0672 reg = <0 0x11018000 0 0x100>;
0673 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>;
0674 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
0675 <&topckgen CLK_TOP_SPI_SEL>,
0676 <&pericfg CLK_PERI_SPI5>;
0677 clock-names = "parent-clk", "sel-clk", "spi-clk";
0678 status = "disabled";
0679 };
0680
0681 uart4: serial@11019000 {
0682 compatible = "mediatek,mt2712-uart",
0683 "mediatek,mt6577-uart";
0684 reg = <0 0x11019000 0 0x400>;
0685 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
0686 clocks = <&baud_clk>, <&sys_clk>;
0687 clock-names = "baud", "bus";
0688 dmas = <&apdma 8
0689 &apdma 9>;
0690 dma-names = "tx", "rx";
0691 status = "disabled";
0692 };
0693
0694 stmmac_axi_setup: stmmac-axi-config {
0695 snps,wr_osr_lmt = <0x7>;
0696 snps,rd_osr_lmt = <0x7>;
0697 snps,blen = <0 0 0 0 16 8 4>;
0698 };
0699
0700 mtl_rx_setup: rx-queues-config {
0701 snps,rx-queues-to-use = <1>;
0702 snps,rx-sched-sp;
0703 queue0 {
0704 snps,dcb-algorithm;
0705 snps,map-to-dma-channel = <0x0>;
0706 snps,priority = <0x0>;
0707 };
0708 };
0709
0710 mtl_tx_setup: tx-queues-config {
0711 snps,tx-queues-to-use = <3>;
0712 snps,tx-sched-wrr;
0713 queue0 {
0714 snps,weight = <0x10>;
0715 snps,dcb-algorithm;
0716 snps,priority = <0x0>;
0717 };
0718 queue1 {
0719 snps,weight = <0x11>;
0720 snps,dcb-algorithm;
0721 snps,priority = <0x1>;
0722 };
0723 queue2 {
0724 snps,weight = <0x12>;
0725 snps,dcb-algorithm;
0726 snps,priority = <0x2>;
0727 };
0728 };
0729
0730 eth: ethernet@1101c000 {
0731 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
0732 reg = <0 0x1101c000 0 0x1300>;
0733 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
0734 interrupt-names = "macirq";
0735 mac-address = [00 55 7b b5 7d f7];
0736 clock-names = "axi",
0737 "apb",
0738 "mac_main",
0739 "ptp_ref",
0740 "rmii_internal";
0741 clocks = <&pericfg CLK_PERI_GMAC>,
0742 <&pericfg CLK_PERI_GMAC_PCLK>,
0743 <&topckgen CLK_TOP_ETHER_125M_SEL>,
0744 <&topckgen CLK_TOP_ETHER_50M_SEL>,
0745 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
0746 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
0747 <&topckgen CLK_TOP_ETHER_50M_SEL>,
0748 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
0749 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
0750 <&topckgen CLK_TOP_APLL1_D3>,
0751 <&topckgen CLK_TOP_ETHERPLL_50M>;
0752 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
0753 mediatek,pericfg = <&pericfg>;
0754 snps,axi-config = <&stmmac_axi_setup>;
0755 snps,mtl-rx-config = <&mtl_rx_setup>;
0756 snps,mtl-tx-config = <&mtl_tx_setup>;
0757 snps,txpbl = <1>;
0758 snps,rxpbl = <1>;
0759 clk_csr = <0>;
0760 status = "disabled";
0761 };
0762
0763 mmc0: mmc@11230000 {
0764 compatible = "mediatek,mt2712-mmc";
0765 reg = <0 0x11230000 0 0x1000>;
0766 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
0767 clocks = <&pericfg CLK_PERI_MSDC30_0>,
0768 <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
0769 <&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
0770 <&pericfg CLK_PERI_MSDC50_0_EN>;
0771 clock-names = "source", "hclk", "bus_clk", "source_cg";
0772 status = "disabled";
0773 };
0774
0775 mmc1: mmc@11240000 {
0776 compatible = "mediatek,mt2712-mmc";
0777 reg = <0 0x11240000 0 0x1000>;
0778 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
0779 clocks = <&pericfg CLK_PERI_MSDC30_1>,
0780 <&topckgen CLK_TOP_AXI_SEL>,
0781 <&pericfg CLK_PERI_MSDC30_1_EN>;
0782 clock-names = "source", "hclk", "source_cg";
0783 status = "disabled";
0784 };
0785
0786 mmc2: mmc@11250000 {
0787 compatible = "mediatek,mt2712-mmc";
0788 reg = <0 0x11250000 0 0x1000>;
0789 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
0790 clocks = <&pericfg CLK_PERI_MSDC30_2>,
0791 <&topckgen CLK_TOP_AXI_SEL>,
0792 <&pericfg CLK_PERI_MSDC30_2_EN>;
0793 clock-names = "source", "hclk", "source_cg";
0794 status = "disabled";
0795 };
0796
0797 ssusb: usb@11271000 {
0798 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
0799 reg = <0 0x11271000 0 0x3000>,
0800 <0 0x11280700 0 0x0100>;
0801 reg-names = "mac", "ippc";
0802 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
0803 phys = <&u2port0 PHY_TYPE_USB2>,
0804 <&u2port1 PHY_TYPE_USB2>;
0805 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
0806 clocks = <&topckgen CLK_TOP_USB30_SEL>;
0807 clock-names = "sys_ck";
0808 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
0809 #address-cells = <2>;
0810 #size-cells = <2>;
0811 ranges;
0812 status = "disabled";
0813
0814 usb_host0: usb@11270000 {
0815 compatible = "mediatek,mt2712-xhci",
0816 "mediatek,mtk-xhci";
0817 reg = <0 0x11270000 0 0x1000>;
0818 reg-names = "mac";
0819 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>;
0820 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
0821 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
0822 clock-names = "sys_ck", "ref_ck";
0823 status = "disabled";
0824 };
0825 };
0826
0827 u3phy0: t-phy@11290000 {
0828 compatible = "mediatek,mt2712-tphy",
0829 "mediatek,generic-tphy-v2";
0830 #address-cells = <1>;
0831 #size-cells = <1>;
0832 ranges = <0 0 0x11290000 0x9000>;
0833 status = "okay";
0834
0835 u2port0: usb-phy@0 {
0836 reg = <0x0 0x700>;
0837 clocks = <&clk26m>;
0838 clock-names = "ref";
0839 #phy-cells = <1>;
0840 status = "okay";
0841 };
0842
0843 u2port1: usb-phy@8000 {
0844 reg = <0x8000 0x700>;
0845 clocks = <&clk26m>;
0846 clock-names = "ref";
0847 #phy-cells = <1>;
0848 status = "okay";
0849 };
0850
0851 u3port0: usb-phy@8700 {
0852 reg = <0x8700 0x900>;
0853 clocks = <&clk26m>;
0854 clock-names = "ref";
0855 #phy-cells = <1>;
0856 status = "okay";
0857 };
0858 };
0859
0860 ssusb1: usb@112c1000 {
0861 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
0862 reg = <0 0x112c1000 0 0x3000>,
0863 <0 0x112d0700 0 0x0100>;
0864 reg-names = "mac", "ippc";
0865 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>;
0866 phys = <&u2port2 PHY_TYPE_USB2>,
0867 <&u2port3 PHY_TYPE_USB2>,
0868 <&u3port1 PHY_TYPE_USB3>;
0869 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
0870 clocks = <&topckgen CLK_TOP_USB30_SEL>;
0871 clock-names = "sys_ck";
0872 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
0873 #address-cells = <2>;
0874 #size-cells = <2>;
0875 ranges;
0876 status = "disabled";
0877
0878 usb_host1: usb@112c0000 {
0879 compatible = "mediatek,mt2712-xhci",
0880 "mediatek,mtk-xhci";
0881 reg = <0 0x112c0000 0 0x1000>;
0882 reg-names = "mac";
0883 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
0884 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
0885 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
0886 clock-names = "sys_ck", "ref_ck";
0887 status = "disabled";
0888 };
0889 };
0890
0891 u3phy1: t-phy@112e0000 {
0892 compatible = "mediatek,mt2712-tphy",
0893 "mediatek,generic-tphy-v2";
0894 #address-cells = <1>;
0895 #size-cells = <1>;
0896 ranges = <0 0 0x112e0000 0x9000>;
0897 status = "okay";
0898
0899 u2port2: usb-phy@0 {
0900 reg = <0x0 0x700>;
0901 clocks = <&clk26m>;
0902 clock-names = "ref";
0903 #phy-cells = <1>;
0904 status = "okay";
0905 };
0906
0907 u2port3: usb-phy@8000 {
0908 reg = <0x8000 0x700>;
0909 clocks = <&clk26m>;
0910 clock-names = "ref";
0911 #phy-cells = <1>;
0912 status = "okay";
0913 };
0914
0915 u3port1: usb-phy@8700 {
0916 reg = <0x8700 0x900>;
0917 clocks = <&clk26m>;
0918 clock-names = "ref";
0919 #phy-cells = <1>;
0920 status = "okay";
0921 };
0922 };
0923
0924 pcie1: pcie@112ff000 {
0925 compatible = "mediatek,mt2712-pcie";
0926 device_type = "pci";
0927 reg = <0 0x112ff000 0 0x1000>;
0928 reg-names = "port1";
0929 linux,pci-domain = <1>;
0930 #address-cells = <3>;
0931 #size-cells = <2>;
0932 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0933 interrupt-names = "pcie_irq";
0934 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
0935 <&pericfg CLK_PERI_PCIE1>;
0936 clock-names = "sys_ck1", "ahb_ck1";
0937 phys = <&u3port1 PHY_TYPE_PCIE>;
0938 phy-names = "pcie-phy1";
0939 bus-range = <0x00 0xff>;
0940 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
0941 status = "disabled";
0942
0943 #interrupt-cells = <1>;
0944 interrupt-map-mask = <0 0 0 7>;
0945 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
0946 <0 0 0 2 &pcie_intc1 1>,
0947 <0 0 0 3 &pcie_intc1 2>,
0948 <0 0 0 4 &pcie_intc1 3>;
0949 pcie_intc1: interrupt-controller {
0950 interrupt-controller;
0951 #address-cells = <0>;
0952 #interrupt-cells = <1>;
0953 };
0954 };
0955
0956 pcie0: pcie@11700000 {
0957 compatible = "mediatek,mt2712-pcie";
0958 device_type = "pci";
0959 reg = <0 0x11700000 0 0x1000>;
0960 reg-names = "port0";
0961 linux,pci-domain = <0>;
0962 #address-cells = <3>;
0963 #size-cells = <2>;
0964 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0965 interrupt-names = "pcie_irq";
0966 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
0967 <&pericfg CLK_PERI_PCIE0>;
0968 clock-names = "sys_ck0", "ahb_ck0";
0969 phys = <&u3port0 PHY_TYPE_PCIE>;
0970 phy-names = "pcie-phy0";
0971 bus-range = <0x00 0xff>;
0972 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
0973 status = "disabled";
0974
0975 #interrupt-cells = <1>;
0976 interrupt-map-mask = <0 0 0 7>;
0977 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
0978 <0 0 0 2 &pcie_intc0 1>,
0979 <0 0 0 3 &pcie_intc0 2>,
0980 <0 0 0 4 &pcie_intc0 3>;
0981 pcie_intc0: interrupt-controller {
0982 interrupt-controller;
0983 #address-cells = <0>;
0984 #interrupt-cells = <1>;
0985 };
0986 };
0987
0988 mfgcfg: syscon@13000000 {
0989 compatible = "mediatek,mt2712-mfgcfg", "syscon";
0990 reg = <0 0x13000000 0 0x1000>;
0991 #clock-cells = <1>;
0992 };
0993
0994 mmsys: syscon@14000000 {
0995 compatible = "mediatek,mt2712-mmsys", "syscon";
0996 reg = <0 0x14000000 0 0x1000>;
0997 #clock-cells = <1>;
0998 };
0999
1000 larb0: larb@14021000 {
1001 compatible = "mediatek,mt2712-smi-larb";
1002 reg = <0 0x14021000 0 0x1000>;
1003 mediatek,smi = <&smi_common0>;
1004 mediatek,larb-id = <0>;
1005 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1006 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1007 <&mmsys CLK_MM_SMI_LARB0>;
1008 clock-names = "apb", "smi";
1009 };
1010
1011 smi_common0: smi@14022000 {
1012 compatible = "mediatek,mt2712-smi-common";
1013 reg = <0 0x14022000 0 0x1000>;
1014 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1015 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1016 <&mmsys CLK_MM_SMI_COMMON>;
1017 clock-names = "apb", "smi";
1018 };
1019
1020 larb4: larb@14027000 {
1021 compatible = "mediatek,mt2712-smi-larb";
1022 reg = <0 0x14027000 0 0x1000>;
1023 mediatek,smi = <&smi_common1>;
1024 mediatek,larb-id = <4>;
1025 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1026 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1027 <&mmsys CLK_MM_SMI_LARB4>;
1028 clock-names = "apb", "smi";
1029 };
1030
1031 larb5: larb@14030000 {
1032 compatible = "mediatek,mt2712-smi-larb";
1033 reg = <0 0x14030000 0 0x1000>;
1034 mediatek,smi = <&smi_common1>;
1035 mediatek,larb-id = <5>;
1036 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1037 clocks = <&mmsys CLK_MM_SMI_LARB5>,
1038 <&mmsys CLK_MM_SMI_LARB5>;
1039 clock-names = "apb", "smi";
1040 };
1041
1042 smi_common1: smi@14031000 {
1043 compatible = "mediatek,mt2712-smi-common";
1044 reg = <0 0x14031000 0 0x1000>;
1045 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1046 clocks = <&mmsys CLK_MM_SMI_COMMON1>,
1047 <&mmsys CLK_MM_SMI_COMMON1>;
1048 clock-names = "apb", "smi";
1049 };
1050
1051 larb7: larb@14032000 {
1052 compatible = "mediatek,mt2712-smi-larb";
1053 reg = <0 0x14032000 0 0x1000>;
1054 mediatek,smi = <&smi_common1>;
1055 mediatek,larb-id = <7>;
1056 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1057 clocks = <&mmsys CLK_MM_SMI_LARB7>,
1058 <&mmsys CLK_MM_SMI_LARB7>;
1059 clock-names = "apb", "smi";
1060 };
1061
1062 imgsys: syscon@15000000 {
1063 compatible = "mediatek,mt2712-imgsys", "syscon";
1064 reg = <0 0x15000000 0 0x1000>;
1065 #clock-cells = <1>;
1066 };
1067
1068 larb2: larb@15001000 {
1069 compatible = "mediatek,mt2712-smi-larb";
1070 reg = <0 0x15001000 0 0x1000>;
1071 mediatek,smi = <&smi_common0>;
1072 mediatek,larb-id = <2>;
1073 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
1074 clocks = <&imgsys CLK_IMG_SMI_LARB2>,
1075 <&imgsys CLK_IMG_SMI_LARB2>;
1076 clock-names = "apb", "smi";
1077 };
1078
1079 bdpsys: syscon@15010000 {
1080 compatible = "mediatek,mt2712-bdpsys", "syscon";
1081 reg = <0 0x15010000 0 0x1000>;
1082 #clock-cells = <1>;
1083 };
1084
1085 vdecsys: syscon@16000000 {
1086 compatible = "mediatek,mt2712-vdecsys", "syscon";
1087 reg = <0 0x16000000 0 0x1000>;
1088 #clock-cells = <1>;
1089 };
1090
1091 larb1: larb@16010000 {
1092 compatible = "mediatek,mt2712-smi-larb";
1093 reg = <0 0x16010000 0 0x1000>;
1094 mediatek,smi = <&smi_common0>;
1095 mediatek,larb-id = <1>;
1096 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
1097 clocks = <&vdecsys CLK_VDEC_CKEN>,
1098 <&vdecsys CLK_VDEC_LARB1_CKEN>;
1099 clock-names = "apb", "smi";
1100 };
1101
1102 vencsys: syscon@18000000 {
1103 compatible = "mediatek,mt2712-vencsys", "syscon";
1104 reg = <0 0x18000000 0 0x1000>;
1105 #clock-cells = <1>;
1106 };
1107
1108 larb3: larb@18001000 {
1109 compatible = "mediatek,mt2712-smi-larb";
1110 reg = <0 0x18001000 0 0x1000>;
1111 mediatek,smi = <&smi_common0>;
1112 mediatek,larb-id = <3>;
1113 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1114 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1115 <&vencsys CLK_VENC_VENC>;
1116 clock-names = "apb", "smi";
1117 };
1118
1119 larb6: larb@18002000 {
1120 compatible = "mediatek,mt2712-smi-larb";
1121 reg = <0 0x18002000 0 0x1000>;
1122 mediatek,smi = <&smi_common0>;
1123 mediatek,larb-id = <6>;
1124 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1125 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1126 <&vencsys CLK_VENC_VENC>;
1127 clock-names = "apb", "smi";
1128 };
1129
1130 jpgdecsys: syscon@19000000 {
1131 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
1132 reg = <0 0x19000000 0 0x1000>;
1133 #clock-cells = <1>;
1134 };
1135 };
1136
