0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2020 Marvell International Ltd.
0004 *
0005 * Device tree for the CN9132-DB board.
0006 */
0007
0008 #include "cn9131-db.dtsi"
0009
0010 / {
0011 compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
0012 "marvell,armada-ap807-quad", "marvell,armada-ap807";
0013
0014 aliases {
0015 gpio5 = &cp2_gpio1;
0016 gpio6 = &cp2_gpio2;
0017 ethernet5 = &cp2_eth0;
0018 };
0019
0020 cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
0021 compatible = "regulator-fixed";
0022 regulator-name = "cp2-xhci0-vbus";
0023 regulator-min-microvolt = <5000000>;
0024 regulator-max-microvolt = <5000000>;
0025 enable-active-high;
0026 gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
0027 };
0028
0029 cp2_usb3_0_phy0: cp2_usb3_phy0 {
0030 compatible = "usb-nop-xceiv";
0031 vcc-supply = <&cp2_reg_usb3_vbus0>;
0032 };
0033
0034 cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
0035 compatible = "regulator-fixed";
0036 regulator-name = "cp2-xhci1-vbus";
0037 regulator-min-microvolt = <5000000>;
0038 regulator-max-microvolt = <5000000>;
0039 enable-active-high;
0040 gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
0041 };
0042
0043 cp2_usb3_0_phy1: cp2_usb3_phy1 {
0044 compatible = "usb-nop-xceiv";
0045 vcc-supply = <&cp2_reg_usb3_vbus1>;
0046 };
0047
0048 cp2_reg_sd_vccq: cp2_sd_vccq@0 {
0049 compatible = "regulator-gpio";
0050 regulator-name = "cp2_sd_vcc";
0051 regulator-min-microvolt = <1800000>;
0052 regulator-max-microvolt = <3300000>;
0053 gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
0054 states = <1800000 0x1 3300000 0x0>;
0055 };
0056
0057 cp2_sfp_eth0: sfp-eth0 {
0058 compatible = "sff,sfp";
0059 i2c-bus = <&cp2_sfpp0_i2c>;
0060 los-gpios = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
0061 mod-def0-gpios = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
0062 tx-disable-gpios = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
0063 tx-fault-gpios = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
0064 /*
0065 * SFP cages are unconnected on early PCBs because of an the I2C
0066 * lanes not being connected. Prevent the port for being
0067 * unusable by disabling the SFP node.
0068 */
0069 status = "disabled";
0070 };
0071 };
0072
0073 /*
0074 * Instantiate the second slave CP115
0075 */
0076
0077 #define CP11X_NAME cp2
0078 #define CP11X_BASE f6000000
0079 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
0080 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
0081 #define CP11X_PCIE0_BASE f6600000
0082 #define CP11X_PCIE1_BASE f6620000
0083 #define CP11X_PCIE2_BASE f6640000
0084
0085 #include "armada-cp115.dtsi"
0086
0087 #undef CP11X_NAME
0088 #undef CP11X_BASE
0089 #undef CP11X_PCIEx_MEM_BASE
0090 #undef CP11X_PCIEx_MEM_SIZE
0091 #undef CP11X_PCIE0_BASE
0092 #undef CP11X_PCIE1_BASE
0093 #undef CP11X_PCIE2_BASE
0094
0095 &cp2_crypto {
0096 status = "disabled";
0097 };
0098
0099 &cp2_ethernet {
0100 status = "okay";
0101 };
0102
0103 /* SLM-1521-V2, CON9 */
0104 &cp2_eth0 {
0105 status = "disabled";
0106 phy-mode = "10gbase-r";
0107 /* Generic PHY, providing serdes lanes */
0108 phys = <&cp2_comphy4 0>;
0109 managed = "in-band-status";
0110 sfp = <&cp2_sfp_eth0>;
0111 };
0112
0113 &cp2_gpio1 {
0114 status = "okay";
0115 };
0116
0117 &cp2_gpio2 {
0118 status = "okay";
0119 };
0120
0121 &cp2_i2c0 {
0122 clock-frequency = <100000>;
0123
0124 /* SLM-1521-V2 - U3 */
0125 i2c-mux@72 {
0126 compatible = "nxp,pca9544";
0127 #address-cells = <1>;
0128 #size-cells = <0>;
0129 reg = <0x72>;
0130 cp2_sfpp0_i2c: i2c@0 {
0131 #address-cells = <1>;
0132 #size-cells = <0>;
0133 reg = <0>;
0134 };
0135
0136 i2c@1 {
0137 #address-cells = <1>;
0138 #size-cells = <0>;
0139 reg = <1>;
0140 /* U12 */
0141 cp2_module_expander1: pca9555@21 {
0142 compatible = "nxp,pca9555";
0143 pinctrl-names = "default";
0144 gpio-controller;
0145 #gpio-cells = <2>;
0146 reg = <0x21>;
0147 };
0148 };
0149 };
0150 };
0151
0152 /* SLM-1521-V2, CON6 */
0153 &cp2_pcie0 {
0154 status = "okay";
0155 num-lanes = <2>;
0156 num-viewport = <8>;
0157 /* Generic PHY, providing serdes lanes */
0158 phys = <&cp2_comphy0 0
0159 &cp2_comphy1 0>;
0160 };
0161
0162 /* SLM-1521-V2, CON8 */
0163 &cp2_pcie2 {
0164 status = "okay";
0165 num-lanes = <1>;
0166 num-viewport = <8>;
0167 /* Generic PHY, providing serdes lanes */
0168 phys = <&cp2_comphy5 2>;
0169 };
0170
0171 &cp2_sata0 {
0172 status = "okay";
0173
0174 /* SLM-1521-V2, CON4 */
0175 sata-port@0 {
0176 /* Generic PHY, providing serdes lanes */
0177 phys = <&cp2_comphy2 0>;
0178 };
0179 };
0180
0181 /* CON 2 on SLM-1683 - microSD */
0182 &cp2_sdhci0 {
0183 status = "okay";
0184 pinctrl-names = "default";
0185 pinctrl-0 = <&cp2_sdhci_pins>;
0186 bus-width = <4>;
0187 cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
0188 vqmmc-supply = <&cp2_reg_sd_vccq>;
0189 };
0190
0191 &cp2_syscon0 {
0192 cp2_pinctrl: pinctrl {
0193 compatible = "marvell,cp115-standalone-pinctrl";
0194
0195 cp2_i2c0_pins: cp2-i2c-pins-0 {
0196 marvell,pins = "mpp37", "mpp38";
0197 marvell,function = "i2c0";
0198 };
0199 cp2_sdhci_pins: cp2-sdhi-pins-0 {
0200 marvell,pins = "mpp56", "mpp57", "mpp58",
0201 "mpp59", "mpp60", "mpp61";
0202 marvell,function = "sdio";
0203 };
0204 };
0205 };
0206
0207 &cp2_utmi {
0208 status = "okay";
0209 };
0210
0211 &cp2_usb3_0 {
0212 status = "okay";
0213 usb-phy = <&cp2_usb3_0_phy0>;
0214 phys = <&cp2_utmi0>;
0215 phy-names = "usb";
0216 dr_mode = "host";
0217 };
0218
0219 /* SLM-1521-V2, CON11 */
0220 &cp2_usb3_1 {
0221 status = "okay";
0222 usb-phy = <&cp2_usb3_0_phy1>;
0223 /* Generic PHY, providing serdes lanes */
0224 phys = <&cp2_comphy3 1>, <&cp2_utmi1>;
0225 phy-names = "usb", "utmi";
0226 dr_mode = "host";
0227 };
