0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2019 Marvell International Ltd.
0004 *
0005 * Device tree for the CN9130 SoC.
0006 */
0007
0008 #include "armada-ap807-quad.dtsi"
0009
0010 / {
0011 model = "Marvell Armada CN9130 SoC";
0012 compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
0013 "marvell,armada-ap807";
0014
0015 aliases {
0016 gpio1 = &cp0_gpio1;
0017 gpio2 = &cp0_gpio2;
0018 spi1 = &cp0_spi0;
0019 spi2 = &cp0_spi1;
0020 };
0021 };
0022
0023 /*
0024 * Instantiate the internal CP115
0025 */
0026
0027 #define CP11X_NAME cp0
0028 #define CP11X_BASE f2000000
0029 #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
0030 0xe0000000 + ((iface - 1) * 0x1000000))
0031 #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
0032 #define CP11X_PCIE0_BASE f2600000
0033 #define CP11X_PCIE1_BASE f2620000
0034 #define CP11X_PCIE2_BASE f2640000
0035
0036 #include "armada-cp115.dtsi"
0037
0038 #undef CP11X_NAME
0039 #undef CP11X_BASE
0040 #undef CP11X_PCIEx_MEM_BASE
0041 #undef CP11X_PCIEx_MEM_SIZE
0042 #undef CP11X_PCIE0_BASE
0043 #undef CP11X_PCIE1_BASE
0044 #undef CP11X_PCIE2_BASE
0045
0046 &cp0_gpio1 {
0047 status = "okay";
0048 };
0049
0050 &cp0_gpio2 {
0051 status = "okay";
0052 };
