0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2019 Marvell International Ltd.
0004 *
0005 * Device tree for the CN9130-DB board.
0006 */
0007
0008 #include "cn9130.dtsi"
0009
0010 #include <dt-bindings/gpio/gpio.h>
0011
0012 / {
0013 chosen {
0014 stdout-path = "serial0:115200n8";
0015 };
0016
0017 aliases {
0018 gpio1 = &cp0_gpio1;
0019 gpio2 = &cp0_gpio2;
0020 i2c0 = &cp0_i2c0;
0021 ethernet0 = &cp0_eth0;
0022 ethernet1 = &cp0_eth1;
0023 ethernet2 = &cp0_eth2;
0024 spi1 = &cp0_spi0;
0025 spi2 = &cp0_spi1;
0026 };
0027
0028 memory@0 {
0029 device_type = "memory";
0030 reg = <0x0 0x0 0x0 0x80000000>;
0031 };
0032
0033 ap0_reg_sd_vccq: ap0_sd_vccq@0 {
0034 compatible = "regulator-gpio";
0035 regulator-name = "ap0_sd_vccq";
0036 regulator-min-microvolt = <1800000>;
0037 regulator-max-microvolt = <3300000>;
0038 gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
0039 states = <1800000 0x1 3300000 0x0>;
0040 };
0041
0042 cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
0043 compatible = "regulator-fixed";
0044 regulator-name = "cp0-xhci0-vbus";
0045 regulator-min-microvolt = <5000000>;
0046 regulator-max-microvolt = <5000000>;
0047 enable-active-high;
0048 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
0049 };
0050
0051 cp0_usb3_0_phy0: cp0_usb3_phy@0 {
0052 compatible = "usb-nop-xceiv";
0053 vcc-supply = <&cp0_reg_usb3_vbus0>;
0054 };
0055
0056 cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
0057 compatible = "regulator-fixed";
0058 regulator-name = "cp0-xhci1-vbus";
0059 regulator-min-microvolt = <5000000>;
0060 regulator-max-microvolt = <5000000>;
0061 enable-active-high;
0062 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
0063 };
0064
0065 cp0_usb3_0_phy1: cp0_usb3_phy@1 {
0066 compatible = "usb-nop-xceiv";
0067 vcc-supply = <&cp0_reg_usb3_vbus1>;
0068 };
0069
0070 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
0071 compatible = "regulator-gpio";
0072 regulator-name = "cp0_sd_vccq";
0073 regulator-min-microvolt = <1800000>;
0074 regulator-max-microvolt = <3300000>;
0075 gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
0076 states = <1800000 0x1
0077 3300000 0x0>;
0078 };
0079
0080 cp0_reg_sd_vcc: cp0_sd_vcc@0 {
0081 compatible = "regulator-fixed";
0082 regulator-name = "cp0_sd_vcc";
0083 regulator-min-microvolt = <3300000>;
0084 regulator-max-microvolt = <3300000>;
0085 gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
0086 enable-active-high;
0087 regulator-always-on;
0088 };
0089
0090 cp0_sfp_eth0: sfp-eth@0 {
0091 compatible = "sff,sfp";
0092 i2c-bus = <&cp0_sfpp0_i2c>;
0093 los-gpios = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
0094 mod-def0-gpios = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
0095 tx-disable-gpios = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
0096 tx-fault-gpios = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
0097 /*
0098 * SFP cages are unconnected on early PCBs because of an the I2C
0099 * lanes not being connected. Prevent the port for being
0100 * unusable by disabling the SFP node.
0101 */
0102 status = "disabled";
0103 };
0104 };
0105
0106 &uart0 {
0107 status = "okay";
0108 };
0109
0110 /* on-board eMMC - U9 */
0111 &ap_sdhci0 {
0112 pinctrl-names = "default";
0113 bus-width = <8>;
0114 vqmmc-supply = <&ap0_reg_sd_vccq>;
0115 status = "okay";
0116 };
0117
0118 &cp0_crypto {
0119 status = "disabled";
0120 };
0121
0122 &cp0_ethernet {
0123 status = "okay";
0124 };
0125
0126 /* SLM-1521-V2, CON9 */
0127 &cp0_eth0 {
0128 status = "okay";
0129 phy-mode = "10gbase-r";
0130 /* Generic PHY, providing serdes lanes */
0131 phys = <&cp0_comphy4 0>;
0132 managed = "in-band-status";
0133 sfp = <&cp0_sfp_eth0>;
0134 };
0135
0136 /* CON56 */
0137 &cp0_eth1 {
0138 status = "okay";
0139 phy = <&phy0>;
0140 phy-mode = "rgmii-id";
0141 };
0142
0143 /* CON57 */
0144 &cp0_eth2 {
0145 status = "okay";
0146 phy = <&phy1>;
0147 phy-mode = "rgmii-id";
0148 };
0149
0150 &cp0_gpio1 {
0151 status = "okay";
0152 };
0153
0154 &cp0_gpio2 {
0155 status = "okay";
0156 };
0157
0158 &cp0_i2c0 {
0159 status = "okay";
0160 pinctrl-names = "default";
0161 pinctrl-0 = <&cp0_i2c0_pins>;
0162 clock-frequency = <100000>;
0163
0164 /* U36 */
0165 expander0: pca953x@21 {
0166 compatible = "nxp,pca9555";
0167 pinctrl-names = "default";
0168 gpio-controller;
0169 #gpio-cells = <2>;
0170 reg = <0x21>;
0171 status = "okay";
0172 };
0173
0174 /* U42 */
0175 eeprom0: eeprom@50 {
0176 compatible = "atmel,24c64";
0177 reg = <0x50>;
0178 pagesize = <0x20>;
0179 };
0180
0181 /* U38 */
0182 eeprom1: eeprom@57 {
0183 compatible = "atmel,24c64";
0184 reg = <0x57>;
0185 pagesize = <0x20>;
0186 };
0187 };
0188
0189 &cp0_i2c1 {
0190 status = "okay";
0191 clock-frequency = <100000>;
0192
0193 /* SLM-1521-V2 - U3 */
0194 i2c-mux@72 { /* verify address - depends on dpr */
0195 compatible = "nxp,pca9544";
0196 #address-cells = <1>;
0197 #size-cells = <0>;
0198 reg = <0x72>;
0199 cp0_sfpp0_i2c: i2c@0 {
0200 #address-cells = <1>;
0201 #size-cells = <0>;
0202 reg = <0>;
0203 };
0204
0205 i2c@1 {
0206 #address-cells = <1>;
0207 #size-cells = <0>;
0208 reg = <1>;
0209 /* U12 */
0210 cp0_module_expander1: pca9555@21 {
0211 compatible = "nxp,pca9555";
0212 pinctrl-names = "default";
0213 gpio-controller;
0214 #gpio-cells = <2>;
0215 reg = <0x21>;
0216 };
0217
0218 };
0219 };
0220 };
0221
0222 &cp0_mdio {
0223 status = "okay";
0224
0225 phy0: ethernet-phy@0 {
0226 reg = <0>;
0227 };
0228
0229 phy1: ethernet-phy@1 {
0230 reg = <1>;
0231 };
0232 };
0233
0234 /* U54 */
0235 &cp0_nand_controller {
0236 status = "disabled";
0237 pinctrl-names = "default";
0238 pinctrl-0 = <&nand_pins &nand_rb>;
0239
0240 nand@0 {
0241 reg = <0>;
0242 label = "main-storage";
0243 nand-rb = <0>;
0244 nand-ecc-mode = "hw";
0245 nand-on-flash-bbt;
0246 nand-ecc-strength = <8>;
0247 nand-ecc-step-size = <512>;
0248
0249 partitions {
0250 compatible = "fixed-partitions";
0251 #address-cells = <1>;
0252 #size-cells = <1>;
0253
0254 partition@0 {
0255 label = "U-Boot";
0256 reg = <0 0x200000>;
0257 };
0258 partition@200000 {
0259 label = "Linux";
0260 reg = <0x200000 0xe00000>;
0261 };
0262 partition@1000000 {
0263 label = "Filesystem";
0264 reg = <0x1000000 0x3f000000>;
0265 };
0266 };
0267 };
0268 };
0269
0270 /* SLM-1521-V2, CON6 */
0271 &cp0_pcie0 {
0272 status = "okay";
0273 num-lanes = <4>;
0274 num-viewport = <8>;
0275 /* Generic PHY, providing serdes lanes */
0276 phys = <&cp0_comphy0 0
0277 &cp0_comphy1 0
0278 &cp0_comphy2 0
0279 &cp0_comphy3 0>;
0280 };
0281
0282 &cp0_sata0 {
0283 status = "okay";
0284
0285 /* SLM-1521-V2, CON2 */
0286 sata-port@1 {
0287 status = "okay";
0288 /* Generic PHY, providing serdes lanes */
0289 phys = <&cp0_comphy5 1>;
0290 };
0291 };
0292
0293 /* CON 28 */
0294 &cp0_sdhci0 {
0295 status = "okay";
0296 pinctrl-names = "default";
0297 pinctrl-0 = <&cp0_sdhci_pins
0298 &cp0_sdhci_cd_pins>;
0299 bus-width = <4>;
0300 cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
0301 no-1-8-v;
0302 vqmmc-supply = <&cp0_reg_sd_vccq>;
0303 vmmc-supply = <&cp0_reg_sd_vcc>;
0304 };
0305
0306 /* U55 */
0307 &cp0_spi1 {
0308 status = "disabled";
0309 pinctrl-names = "default";
0310 pinctrl-0 = <&cp0_spi0_pins>;
0311 reg = <0x700680 0x50>;
0312
0313 flash@0 {
0314 #address-cells = <0x1>;
0315 #size-cells = <0x1>;
0316 compatible = "jedec,spi-nor";
0317 reg = <0x0>;
0318 /* On-board MUX does not allow higher frequencies */
0319 spi-max-frequency = <40000000>;
0320
0321 partitions {
0322 compatible = "fixed-partitions";
0323 #address-cells = <1>;
0324 #size-cells = <1>;
0325
0326 partition@0 {
0327 label = "U-Boot-0";
0328 reg = <0x0 0x200000>;
0329 };
0330
0331 partition@400000 {
0332 label = "Filesystem-0";
0333 reg = <0x200000 0xe00000>;
0334 };
0335 };
0336 };
0337 };
0338
0339 &cp0_syscon0 {
0340 cp0_pinctrl: pinctrl {
0341 compatible = "marvell,cp115-standalone-pinctrl";
0342
0343 cp0_i2c0_pins: cp0-i2c-pins-0 {
0344 marvell,pins = "mpp37", "mpp38";
0345 marvell,function = "i2c0";
0346 };
0347 cp0_i2c1_pins: cp0-i2c-pins-1 {
0348 marvell,pins = "mpp35", "mpp36";
0349 marvell,function = "i2c1";
0350 };
0351 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
0352 marvell,pins = "mpp0", "mpp1", "mpp2",
0353 "mpp3", "mpp4", "mpp5",
0354 "mpp6", "mpp7", "mpp8",
0355 "mpp9", "mpp10", "mpp11";
0356 marvell,function = "ge0";
0357 };
0358 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
0359 marvell,pins = "mpp44", "mpp45", "mpp46",
0360 "mpp47", "mpp48", "mpp49",
0361 "mpp50", "mpp51", "mpp52",
0362 "mpp53", "mpp54", "mpp55";
0363 marvell,function = "ge1";
0364 };
0365 cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
0366 marvell,pins = "mpp43";
0367 marvell,function = "gpio";
0368 };
0369 cp0_sdhci_pins: cp0-sdhi-pins-0 {
0370 marvell,pins = "mpp56", "mpp57", "mpp58",
0371 "mpp59", "mpp60", "mpp61";
0372 marvell,function = "sdio";
0373 };
0374 cp0_spi0_pins: cp0-spi-pins-0 {
0375 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
0376 marvell,function = "spi1";
0377 };
0378 nand_pins: nand-pins {
0379 marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
0380 "mpp19", "mpp20", "mpp21", "mpp22",
0381 "mpp23", "mpp24", "mpp25", "mpp26",
0382 "mpp27";
0383 marvell,function = "dev";
0384 };
0385 nand_rb: nand-rb {
0386 marvell,pins = "mpp13";
0387 marvell,function = "nf";
0388 };
0389 };
0390 };
0391
0392 &cp0_utmi {
0393 status = "okay";
0394 };
0395
0396 &cp0_usb3_0 {
0397 status = "okay";
0398 usb-phy = <&cp0_usb3_0_phy0>;
0399 phys = <&cp0_utmi0>;
0400 phy-names = "utmi";
0401 dr_mode = "host";
0402 };
0403
0404 &cp0_usb3_1 {
0405 status = "okay";
0406 usb-phy = <&cp0_usb3_0_phy1>;
0407 phys = <&cp0_utmi1>;
0408 phy-names = "utmi";
0409 dr_mode = "host";
0410 };
