0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright (C) 2020 Marvell International Ltd.
0004 */
0005
0006 #include "cn9130.dtsi" /* include SoC device tree */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009
0010 / {
0011 chosen {
0012 stdout-path = "serial0:115200n8";
0013 };
0014
0015 aliases {
0016 i2c0 = &cp0_i2c0;
0017 ethernet0 = &cp0_eth0;
0018 ethernet1 = &cp0_eth1;
0019 ethernet2 = &cp0_eth2;
0020 gpio1 = &cp0_gpio1;
0021 gpio2 = &cp0_gpio2;
0022 };
0023
0024 memory@0 {
0025 device_type = "memory";
0026 reg = <0x0 0x0 0x0 0x80000000>;
0027 };
0028
0029 ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
0030 compatible = "regulator-gpio";
0031 regulator-name = "ap0_mmc_vccq";
0032 regulator-min-microvolt = <1800000>;
0033 regulator-max-microvolt = <3300000>;
0034 gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
0035 states = <1800000 0x1
0036 3300000 0x0>;
0037 };
0038
0039 cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
0040 compatible = "regulator-fixed";
0041 regulator-name = "cp0-xhci1-vbus";
0042 regulator-min-microvolt = <5000000>;
0043 regulator-max-microvolt = <5000000>;
0044 enable-active-high;
0045 gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
0046 };
0047
0048 cp0_usb3_0_phy0: cp0_usb3_phy0 {
0049 compatible = "usb-nop-xceiv";
0050 };
0051
0052 cp0_usb3_0_phy1: cp0_usb3_phy1 {
0053 compatible = "usb-nop-xceiv";
0054 vcc-supply = <&cp0_reg_usb3_vbus1>;
0055 };
0056
0057 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
0058 compatible = "regulator-gpio";
0059 regulator-name = "cp0_sd_vccq";
0060 regulator-min-microvolt = <1800000>;
0061 regulator-max-microvolt = <3300000>;
0062 gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
0063 states = <1800000 0x1
0064 3300000 0x0>;
0065 };
0066
0067 cp0_reg_sd_vcc: cp0_sd_vcc@0 {
0068 compatible = "regulator-fixed";
0069 regulator-name = "cp0_sd_vcc";
0070 regulator-min-microvolt = <3300000>;
0071 regulator-max-microvolt = <3300000>;
0072 gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
0073 enable-active-high;
0074 regulator-always-on;
0075 };
0076
0077 sfp: sfp {
0078 compatible = "sff,sfp";
0079 i2c-bus = <&cp0_i2c1>;
0080 mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
0081 los-gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
0082 tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
0083 tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
0084 maximum-power-milliwatt = <3000>;
0085 status = "okay";
0086 };
0087 };
0088
0089 &uart0 {
0090 status = "okay";
0091 };
0092
0093 /* on-board eMMC U6 */
0094 &ap_sdhci0 {
0095 pinctrl-names = "default";
0096 bus-width = <8>;
0097 status = "okay";
0098 mmc-ddr-1_8v;
0099 vqmmc-supply = <&ap0_reg_mmc_vccq>;
0100 };
0101
0102 &cp0_syscon0 {
0103 cp0_pinctrl: pinctrl {
0104 compatible = "marvell,cp115-standalone-pinctrl";
0105
0106 cp0_i2c0_pins: cp0-i2c-pins-0 {
0107 marvell,pins = "mpp37", "mpp38";
0108 marvell,function = "i2c0";
0109 };
0110 cp0_i2c1_pins: cp0-i2c-pins-1 {
0111 marvell,pins = "mpp35", "mpp36";
0112 marvell,function = "i2c1";
0113 };
0114 cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
0115 marvell,pins = "mpp55";
0116 marvell,function = "gpio";
0117 };
0118 cp0_sdhci_pins: cp0-sdhi-pins-0 {
0119 marvell,pins = "mpp56", "mpp57", "mpp58",
0120 "mpp59", "mpp60", "mpp61";
0121 marvell,function = "sdio";
0122 };
0123 cp0_spi0_pins: cp0-spi-pins-0 {
0124 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
0125 marvell,function = "spi1";
0126 };
0127 };
0128 };
0129
0130 &cp0_gpio1 {
0131 status = "okay";
0132 };
0133
0134 &cp0_gpio2 {
0135 status = "okay";
0136 };
0137
0138 &cp0_i2c0 {
0139 pinctrl-names = "default";
0140 pinctrl-0 = <&cp0_i2c0_pins>;
0141 status = "okay";
0142 clock-frequency = <100000>;
0143 expander0: mcp23x17@20 {
0144 compatible = "microchip,mcp23017";
0145 gpio-controller;
0146 #gpio-cells = <2>;
0147 reg = <0x20>;
0148 status = "okay";
0149 };
0150 };
0151
0152 &cp0_i2c1 {
0153 pinctrl-names = "default";
0154 pinctrl-0 = <&cp0_i2c1_pins>;
0155 clock-frequency = <100000>;
0156 status = "okay";
0157 };
0158
0159
0160 &cp0_sdhci0 {
0161 pinctrl-names = "default";
0162 pinctrl-0 = <&cp0_sdhci_pins
0163 &cp0_sdhci_cd_pins_crb>;
0164 bus-width = <4>;
0165 cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
0166 vqmmc-supply = <&cp0_reg_sd_vccq>;
0167 vmmc-supply = <&cp0_reg_sd_vcc>;
0168 status = "okay";
0169 };
0170
0171 &cp0_spi1 {
0172 pinctrl-names = "default";
0173 pinctrl-0 = <&cp0_spi0_pins>;
0174 reg = <0x700680 0x50>, /* control */
0175 <0x2000000 0x1000000>; /* CS0 */
0176 status = "okay";
0177
0178 flash@0 {
0179 #address-cells = <0x1>;
0180 #size-cells = <0x1>;
0181 compatible = "jedec,spi-nor";
0182 reg = <0x0>;
0183 /* On-board MUX does not allow higher frequencies */
0184 spi-max-frequency = <40000000>;
0185
0186 partitions {
0187 compatible = "fixed-partitions";
0188 #address-cells = <1>;
0189 #size-cells = <1>;
0190
0191 partition@0 {
0192 label = "U-Boot";
0193 reg = <0x0 0x200000>;
0194 };
0195
0196 partition@400000 {
0197 label = "Filesystem";
0198 reg = <0x200000 0xe00000>;
0199 };
0200 };
0201 };
0202 };
0203
0204 &cp0_mdio {
0205 status = "okay";
0206 phy0: ethernet-phy@0 {
0207 reg = <0>;
0208 };
0209
0210 switch6: switch0@6 {
0211 /* Actual device is MV88E6393X */
0212 compatible = "marvell,mv88e6190";
0213 #address-cells = <1>;
0214 #size-cells = <0>;
0215 reg = <6>;
0216 interrupt-parent = <&cp0_gpio1>;
0217 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
0218 interrupt-controller;
0219 #interrupt-cells = <2>;
0220
0221 dsa,member = <0 0>;
0222
0223 ports {
0224 #address-cells = <1>;
0225 #size-cells = <0>;
0226
0227 port@1 {
0228 reg = <1>;
0229 label = "p1";
0230 phy-handle = <&switch0phy1>;
0231 };
0232
0233 port@2 {
0234 reg = <2>;
0235 label = "p2";
0236 phy-handle = <&switch0phy2>;
0237 };
0238
0239 port@3 {
0240 reg = <3>;
0241 label = "p3";
0242 phy-handle = <&switch0phy3>;
0243 };
0244
0245 port@4 {
0246 reg = <4>;
0247 label = "p4";
0248 phy-handle = <&switch0phy4>;
0249 };
0250
0251 port@5 {
0252 reg = <5>;
0253 label = "p5";
0254 phy-handle = <&switch0phy5>;
0255 };
0256
0257 port@6 {
0258 reg = <6>;
0259 label = "p6";
0260 phy-handle = <&switch0phy6>;
0261 };
0262
0263 port@7 {
0264 reg = <7>;
0265 label = "p7";
0266 phy-handle = <&switch0phy7>;
0267 };
0268
0269 port@8 {
0270 reg = <8>;
0271 label = "p8";
0272 phy-handle = <&switch0phy8>;
0273 };
0274
0275 port@9 {
0276 reg = <9>;
0277 label = "p9";
0278 phy-mode = "10gbase-r";
0279 sfp = <&sfp>;
0280 managed = "in-band-status";
0281 };
0282
0283 port@a {
0284 reg = <10>;
0285 label = "cpu";
0286 ethernet = <&cp0_eth0>;
0287 };
0288
0289 };
0290
0291 mdio {
0292 #address-cells = <1>;
0293 #size-cells = <0>;
0294
0295 switch0phy1: switch0phy1@1 {
0296 reg = <0x1>;
0297 };
0298
0299 switch0phy2: switch0phy2@2 {
0300 reg = <0x2>;
0301 };
0302
0303 switch0phy3: switch0phy3@3 {
0304 reg = <0x3>;
0305 };
0306
0307 switch0phy4: switch0phy4@4 {
0308 reg = <0x4>;
0309 };
0310
0311 switch0phy5: switch0phy5@5 {
0312 reg = <0x5>;
0313 };
0314
0315 switch0phy6: switch0phy6@6 {
0316 reg = <0x6>;
0317 };
0318
0319 switch0phy7: switch0phy7@7 {
0320 reg = <0x7>;
0321 };
0322
0323 switch0phy8: switch0phy8@8 {
0324 reg = <0x8>;
0325 };
0326 };
0327 };
0328 };
0329
0330 &cp0_xmdio {
0331 status = "okay";
0332 nbaset_phy0: ethernet-phy@0 {
0333 compatible = "ethernet-phy-ieee802.3-c45";
0334 reg = <0>;
0335 };
0336 };
0337
0338 &cp0_ethernet {
0339 status = "okay";
0340 };
0341
0342 &cp0_eth0 {
0343 /* This port is connected to 88E6393X switch */
0344 status = "okay";
0345 phy-mode = "10gbase-r";
0346 managed = "in-band-status";
0347 phys = <&cp0_comphy4 0>;
0348 };
0349
0350 &cp0_eth1 {
0351 status = "okay";
0352 phy = <&phy0>;
0353 phy-mode = "rgmii-id";
0354 };
0355
0356 &cp0_eth2 {
0357 /* This port uses "2500base-t" phy-mode */
0358 status = "disabled";
0359 phy = <&nbaset_phy0>;
0360 phys = <&cp0_comphy5 2>;
0361 };
0362
