0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2016 Marvell Technology Group Ltd.
0004 *
0005 * Device Tree file for Marvell Armada CP11x.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
0009 #include <dt-bindings/thermal/thermal.h>
0010
0011 #include "armada-common.dtsi"
0012
0013 #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
0014
0015 / {
0016 /*
0017 * The contents of the node are defined below, in order to
0018 * save one indentation level
0019 */
0020 CP11X_NAME: CP11X_NAME { };
0021
0022 /*
0023 * CPs only have one sensor in the thermal IC.
0024 *
0025 * The cooling maps are empty as there are no cooling devices.
0026 */
0027 thermal-zones {
0028 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
0029 polling-delay-passive = <0>; /* Interrupt driven */
0030 polling-delay = <0>; /* Interrupt driven */
0031
0032 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
0033
0034 trips {
0035 CP11X_LABEL(crit): crit {
0036 temperature = <100000>; /* mC degrees */
0037 hysteresis = <2000>; /* mC degrees */
0038 type = "critical";
0039 };
0040 };
0041
0042 cooling-maps { };
0043 };
0044 };
0045 };
0046
0047 &CP11X_NAME {
0048 #address-cells = <2>;
0049 #size-cells = <2>;
0050 compatible = "simple-bus";
0051 interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
0052 ranges;
0053
0054 config-space@CP11X_BASE {
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057 compatible = "simple-bus";
0058 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
0059
0060 CP11X_LABEL(ethernet): ethernet@0 {
0061 compatible = "marvell,armada-7k-pp22";
0062 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
0063 clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
0064 <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
0065 <&CP11X_LABEL(clk) 1 18>;
0066 clock-names = "pp_clk", "gop_clk",
0067 "mg_clk", "mg_core_clk", "axi_clk";
0068 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
0069 status = "disabled";
0070 dma-coherent;
0071
0072 CP11X_LABEL(eth0): eth0 {
0073 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
0074 <43 IRQ_TYPE_LEVEL_HIGH>,
0075 <47 IRQ_TYPE_LEVEL_HIGH>,
0076 <51 IRQ_TYPE_LEVEL_HIGH>,
0077 <55 IRQ_TYPE_LEVEL_HIGH>,
0078 <59 IRQ_TYPE_LEVEL_HIGH>,
0079 <63 IRQ_TYPE_LEVEL_HIGH>,
0080 <67 IRQ_TYPE_LEVEL_HIGH>,
0081 <71 IRQ_TYPE_LEVEL_HIGH>,
0082 <129 IRQ_TYPE_LEVEL_HIGH>;
0083 interrupt-names = "hif0", "hif1", "hif2",
0084 "hif3", "hif4", "hif5", "hif6", "hif7",
0085 "hif8", "link";
0086 port-id = <0>;
0087 gop-port-id = <0>;
0088 status = "disabled";
0089 };
0090
0091 CP11X_LABEL(eth1): eth1 {
0092 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
0093 <44 IRQ_TYPE_LEVEL_HIGH>,
0094 <48 IRQ_TYPE_LEVEL_HIGH>,
0095 <52 IRQ_TYPE_LEVEL_HIGH>,
0096 <56 IRQ_TYPE_LEVEL_HIGH>,
0097 <60 IRQ_TYPE_LEVEL_HIGH>,
0098 <64 IRQ_TYPE_LEVEL_HIGH>,
0099 <68 IRQ_TYPE_LEVEL_HIGH>,
0100 <72 IRQ_TYPE_LEVEL_HIGH>,
0101 <128 IRQ_TYPE_LEVEL_HIGH>;
0102 interrupt-names = "hif0", "hif1", "hif2",
0103 "hif3", "hif4", "hif5", "hif6", "hif7",
0104 "hif8", "link";
0105 port-id = <1>;
0106 gop-port-id = <2>;
0107 status = "disabled";
0108 };
0109
0110 CP11X_LABEL(eth2): eth2 {
0111 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
0112 <45 IRQ_TYPE_LEVEL_HIGH>,
0113 <49 IRQ_TYPE_LEVEL_HIGH>,
0114 <53 IRQ_TYPE_LEVEL_HIGH>,
0115 <57 IRQ_TYPE_LEVEL_HIGH>,
0116 <61 IRQ_TYPE_LEVEL_HIGH>,
0117 <65 IRQ_TYPE_LEVEL_HIGH>,
0118 <69 IRQ_TYPE_LEVEL_HIGH>,
0119 <73 IRQ_TYPE_LEVEL_HIGH>,
0120 <127 IRQ_TYPE_LEVEL_HIGH>;
0121 interrupt-names = "hif0", "hif1", "hif2",
0122 "hif3", "hif4", "hif5", "hif6", "hif7",
0123 "hif8", "link";
0124 port-id = <2>;
0125 gop-port-id = <3>;
0126 status = "disabled";
0127 };
0128 };
0129
0130 CP11X_LABEL(comphy): phy@120000 {
0131 compatible = "marvell,comphy-cp110";
0132 reg = <0x120000 0x6000>;
0133 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
0134 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
0135 <&CP11X_LABEL(clk) 1 18>;
0136 clock-names = "mg_clk", "mg_core_clk", "axi_clk";
0137 #address-cells = <1>;
0138 #size-cells = <0>;
0139
0140 CP11X_LABEL(comphy0): phy@0 {
0141 reg = <0>;
0142 #phy-cells = <1>;
0143 };
0144
0145 CP11X_LABEL(comphy1): phy@1 {
0146 reg = <1>;
0147 #phy-cells = <1>;
0148 };
0149
0150 CP11X_LABEL(comphy2): phy@2 {
0151 reg = <2>;
0152 #phy-cells = <1>;
0153 };
0154
0155 CP11X_LABEL(comphy3): phy@3 {
0156 reg = <3>;
0157 #phy-cells = <1>;
0158 };
0159
0160 CP11X_LABEL(comphy4): phy@4 {
0161 reg = <4>;
0162 #phy-cells = <1>;
0163 };
0164
0165 CP11X_LABEL(comphy5): phy@5 {
0166 reg = <5>;
0167 #phy-cells = <1>;
0168 };
0169 };
0170
0171 CP11X_LABEL(mdio): mdio@12a200 {
0172 #address-cells = <1>;
0173 #size-cells = <0>;
0174 compatible = "marvell,orion-mdio";
0175 reg = <0x12a200 0x10>;
0176 clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
0177 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
0178 status = "disabled";
0179 };
0180
0181 CP11X_LABEL(xmdio): mdio@12a600 {
0182 #address-cells = <1>;
0183 #size-cells = <0>;
0184 compatible = "marvell,xmdio";
0185 reg = <0x12a600 0x10>;
0186 clocks = <&CP11X_LABEL(clk) 1 5>,
0187 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
0188 status = "disabled";
0189 };
0190
0191 CP11X_LABEL(icu): interrupt-controller@1e0000 {
0192 compatible = "marvell,cp110-icu";
0193 reg = <0x1e0000 0x440>;
0194 #address-cells = <1>;
0195 #size-cells = <1>;
0196
0197 CP11X_LABEL(icu_nsr): interrupt-controller@10 {
0198 compatible = "marvell,cp110-icu-nsr";
0199 reg = <0x10 0x20>;
0200 #interrupt-cells = <2>;
0201 interrupt-controller;
0202 msi-parent = <&gicp>;
0203 };
0204
0205 CP11X_LABEL(icu_sei): interrupt-controller@50 {
0206 compatible = "marvell,cp110-icu-sei";
0207 reg = <0x50 0x10>;
0208 #interrupt-cells = <2>;
0209 interrupt-controller;
0210 msi-parent = <&sei>;
0211 };
0212 };
0213
0214 CP11X_LABEL(rtc): rtc@284000 {
0215 compatible = "marvell,armada-8k-rtc";
0216 reg = <0x284000 0x20>, <0x284080 0x24>;
0217 reg-names = "rtc", "rtc-soc";
0218 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
0219 };
0220
0221 CP11X_LABEL(syscon0): system-controller@440000 {
0222 compatible = "syscon", "simple-mfd";
0223 reg = <0x440000 0x2000>;
0224
0225 CP11X_LABEL(clk): clock {
0226 compatible = "marvell,cp110-clock";
0227 #clock-cells = <2>;
0228 };
0229
0230 CP11X_LABEL(gpio1): gpio@100 {
0231 compatible = "marvell,armada-8k-gpio";
0232 offset = <0x100>;
0233 ngpios = <32>;
0234 gpio-controller;
0235 #gpio-cells = <2>;
0236 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
0237 marvell,pwm-offset = <0x1f0>;
0238 #pwm-cells = <2>;
0239 interrupt-controller;
0240 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
0241 <85 IRQ_TYPE_LEVEL_HIGH>,
0242 <84 IRQ_TYPE_LEVEL_HIGH>,
0243 <83 IRQ_TYPE_LEVEL_HIGH>;
0244 #interrupt-cells = <2>;
0245 clock-names = "core", "axi";
0246 clocks = <&CP11X_LABEL(clk) 1 21>,
0247 <&CP11X_LABEL(clk) 1 17>;
0248 status = "disabled";
0249 };
0250
0251 CP11X_LABEL(gpio2): gpio@140 {
0252 compatible = "marvell,armada-8k-gpio";
0253 offset = <0x140>;
0254 ngpios = <31>;
0255 gpio-controller;
0256 #gpio-cells = <2>;
0257 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
0258 marvell,pwm-offset = <0x1f0>;
0259 #pwm-cells = <2>;
0260 interrupt-controller;
0261 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
0262 <81 IRQ_TYPE_LEVEL_HIGH>,
0263 <80 IRQ_TYPE_LEVEL_HIGH>,
0264 <79 IRQ_TYPE_LEVEL_HIGH>;
0265 #interrupt-cells = <2>;
0266 clock-names = "core", "axi";
0267 clocks = <&CP11X_LABEL(clk) 1 21>,
0268 <&CP11X_LABEL(clk) 1 17>;
0269 status = "disabled";
0270 };
0271 };
0272
0273 CP11X_LABEL(syscon1): system-controller@400000 {
0274 compatible = "syscon", "simple-mfd";
0275 reg = <0x400000 0x1000>;
0276 #address-cells = <1>;
0277 #size-cells = <1>;
0278
0279 CP11X_LABEL(thermal): thermal-sensor@70 {
0280 compatible = "marvell,armada-cp110-thermal";
0281 reg = <0x70 0x10>;
0282 interrupts-extended =
0283 <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
0284 #thermal-sensor-cells = <1>;
0285 };
0286 };
0287
0288 CP11X_LABEL(utmi): utmi@580000 {
0289 compatible = "marvell,cp110-utmi-phy";
0290 reg = <0x580000 0x2000>;
0291 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
0292 #address-cells = <1>;
0293 #size-cells = <0>;
0294 status = "disabled";
0295
0296 CP11X_LABEL(utmi0): usb-phy@0 {
0297 reg = <0>;
0298 #phy-cells = <0>;
0299 };
0300
0301 CP11X_LABEL(utmi1): usb-phy@1 {
0302 reg = <1>;
0303 #phy-cells = <0>;
0304 };
0305 };
0306
0307 CP11X_LABEL(usb3_0): usb@500000 {
0308 compatible = "marvell,armada-8k-xhci",
0309 "generic-xhci";
0310 reg = <0x500000 0x4000>;
0311 dma-coherent;
0312 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
0313 clock-names = "core", "reg";
0314 clocks = <&CP11X_LABEL(clk) 1 22>,
0315 <&CP11X_LABEL(clk) 1 16>;
0316 status = "disabled";
0317 };
0318
0319 CP11X_LABEL(usb3_1): usb@510000 {
0320 compatible = "marvell,armada-8k-xhci",
0321 "generic-xhci";
0322 reg = <0x510000 0x4000>;
0323 dma-coherent;
0324 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
0325 clock-names = "core", "reg";
0326 clocks = <&CP11X_LABEL(clk) 1 23>,
0327 <&CP11X_LABEL(clk) 1 16>;
0328 status = "disabled";
0329 };
0330
0331 CP11X_LABEL(sata0): sata@540000 {
0332 compatible = "marvell,armada-8k-ahci",
0333 "generic-ahci";
0334 reg = <0x540000 0x30000>;
0335 dma-coherent;
0336 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
0337 clocks = <&CP11X_LABEL(clk) 1 15>,
0338 <&CP11X_LABEL(clk) 1 16>;
0339 #address-cells = <1>;
0340 #size-cells = <0>;
0341 status = "disabled";
0342
0343 sata-port@0 {
0344 reg = <0>;
0345 };
0346
0347 sata-port@1 {
0348 reg = <1>;
0349 };
0350 };
0351
0352 CP11X_LABEL(xor0): xor@6a0000 {
0353 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
0354 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
0355 dma-coherent;
0356 msi-parent = <&gic_v2m0>;
0357 clock-names = "core", "reg";
0358 clocks = <&CP11X_LABEL(clk) 1 8>,
0359 <&CP11X_LABEL(clk) 1 14>;
0360 };
0361
0362 CP11X_LABEL(xor1): xor@6c0000 {
0363 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
0364 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
0365 dma-coherent;
0366 msi-parent = <&gic_v2m0>;
0367 clock-names = "core", "reg";
0368 clocks = <&CP11X_LABEL(clk) 1 7>,
0369 <&CP11X_LABEL(clk) 1 14>;
0370 };
0371
0372 CP11X_LABEL(spi0): spi@700600 {
0373 compatible = "marvell,armada-380-spi";
0374 reg = <0x700600 0x50>;
0375 #address-cells = <0x1>;
0376 #size-cells = <0x0>;
0377 clock-names = "core", "axi";
0378 clocks = <&CP11X_LABEL(clk) 1 21>,
0379 <&CP11X_LABEL(clk) 1 17>;
0380 status = "disabled";
0381 };
0382
0383 CP11X_LABEL(spi1): spi@700680 {
0384 compatible = "marvell,armada-380-spi";
0385 reg = <0x700680 0x50>;
0386 #address-cells = <1>;
0387 #size-cells = <0>;
0388 clock-names = "core", "axi";
0389 clocks = <&CP11X_LABEL(clk) 1 21>,
0390 <&CP11X_LABEL(clk) 1 17>;
0391 status = "disabled";
0392 };
0393
0394 CP11X_LABEL(i2c0): i2c@701000 {
0395 compatible = "marvell,mv78230-i2c";
0396 reg = <0x701000 0x20>;
0397 #address-cells = <1>;
0398 #size-cells = <0>;
0399 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
0400 clock-names = "core", "reg";
0401 clocks = <&CP11X_LABEL(clk) 1 21>,
0402 <&CP11X_LABEL(clk) 1 17>;
0403 status = "disabled";
0404 };
0405
0406 CP11X_LABEL(i2c1): i2c@701100 {
0407 compatible = "marvell,mv78230-i2c";
0408 reg = <0x701100 0x20>;
0409 #address-cells = <1>;
0410 #size-cells = <0>;
0411 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
0412 clock-names = "core", "reg";
0413 clocks = <&CP11X_LABEL(clk) 1 21>,
0414 <&CP11X_LABEL(clk) 1 17>;
0415 status = "disabled";
0416 };
0417
0418 CP11X_LABEL(uart0): serial@702000 {
0419 compatible = "snps,dw-apb-uart";
0420 reg = <0x702000 0x100>;
0421 reg-shift = <2>;
0422 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
0423 reg-io-width = <1>;
0424 clock-names = "baudclk", "apb_pclk";
0425 clocks = <&CP11X_LABEL(clk) 1 21>,
0426 <&CP11X_LABEL(clk) 1 17>;
0427 status = "disabled";
0428 };
0429
0430 CP11X_LABEL(uart1): serial@702100 {
0431 compatible = "snps,dw-apb-uart";
0432 reg = <0x702100 0x100>;
0433 reg-shift = <2>;
0434 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
0435 reg-io-width = <1>;
0436 clock-names = "baudclk", "apb_pclk";
0437 clocks = <&CP11X_LABEL(clk) 1 21>,
0438 <&CP11X_LABEL(clk) 1 17>;
0439 status = "disabled";
0440 };
0441
0442 CP11X_LABEL(uart2): serial@702200 {
0443 compatible = "snps,dw-apb-uart";
0444 reg = <0x702200 0x100>;
0445 reg-shift = <2>;
0446 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
0447 reg-io-width = <1>;
0448 clock-names = "baudclk", "apb_pclk";
0449 clocks = <&CP11X_LABEL(clk) 1 21>,
0450 <&CP11X_LABEL(clk) 1 17>;
0451 status = "disabled";
0452 };
0453
0454 CP11X_LABEL(uart3): serial@702300 {
0455 compatible = "snps,dw-apb-uart";
0456 reg = <0x702300 0x100>;
0457 reg-shift = <2>;
0458 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
0459 reg-io-width = <1>;
0460 clock-names = "baudclk", "apb_pclk";
0461 clocks = <&CP11X_LABEL(clk) 1 21>,
0462 <&CP11X_LABEL(clk) 1 17>;
0463 status = "disabled";
0464 };
0465
0466 CP11X_LABEL(nand_controller): nand@720000 {
0467 /*
0468 * Due to the limitation of the pins available
0469 * this controller is only usable on the CPM
0470 * for A7K and on the CPS for A8K.
0471 */
0472 compatible = "marvell,armada-8k-nand-controller",
0473 "marvell,armada370-nand-controller";
0474 reg = <0x720000 0x54>;
0475 #address-cells = <1>;
0476 #size-cells = <0>;
0477 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
0478 clock-names = "core", "reg";
0479 clocks = <&CP11X_LABEL(clk) 1 2>,
0480 <&CP11X_LABEL(clk) 1 17>;
0481 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
0482 status = "disabled";
0483 };
0484
0485 CP11X_LABEL(trng): trng@760000 {
0486 compatible = "marvell,armada-8k-rng",
0487 "inside-secure,safexcel-eip76";
0488 reg = <0x760000 0x7d>;
0489 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
0490 clock-names = "core", "reg";
0491 clocks = <&CP11X_LABEL(clk) 1 25>,
0492 <&CP11X_LABEL(clk) 1 17>;
0493 status = "okay";
0494 };
0495
0496 CP11X_LABEL(sdhci0): mmc@780000 {
0497 compatible = "marvell,armada-cp110-sdhci";
0498 reg = <0x780000 0x300>;
0499 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
0500 clock-names = "core", "axi";
0501 clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
0502 dma-coherent;
0503 status = "disabled";
0504 };
0505
0506 CP11X_LABEL(crypto): crypto@800000 {
0507 compatible = "inside-secure,safexcel-eip197b";
0508 reg = <0x800000 0x200000>;
0509 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
0510 <88 IRQ_TYPE_LEVEL_HIGH>,
0511 <89 IRQ_TYPE_LEVEL_HIGH>,
0512 <90 IRQ_TYPE_LEVEL_HIGH>,
0513 <91 IRQ_TYPE_LEVEL_HIGH>,
0514 <92 IRQ_TYPE_LEVEL_HIGH>;
0515 interrupt-names = "mem", "ring0", "ring1",
0516 "ring2", "ring3", "eip";
0517 clock-names = "core", "reg";
0518 clocks = <&CP11X_LABEL(clk) 1 26>,
0519 <&CP11X_LABEL(clk) 1 17>;
0520 dma-coherent;
0521 };
0522 };
0523
0524 CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
0525 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
0526 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
0527 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
0528 reg-names = "ctrl", "config";
0529 #address-cells = <3>;
0530 #size-cells = <2>;
0531 #interrupt-cells = <1>;
0532 device_type = "pci";
0533 dma-coherent;
0534 msi-parent = <&gic_v2m0>;
0535
0536 bus-range = <0 0xff>;
0537 /* non-prefetchable memory */
0538 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
0539 interrupt-map-mask = <0 0 0 0>;
0540 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
0541 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
0542 num-lanes = <1>;
0543 clock-names = "core", "reg";
0544 clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
0545 status = "disabled";
0546 };
0547
0548 CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
0549 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
0550 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
0551 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
0552 reg-names = "ctrl", "config";
0553 #address-cells = <3>;
0554 #size-cells = <2>;
0555 #interrupt-cells = <1>;
0556 device_type = "pci";
0557 dma-coherent;
0558 msi-parent = <&gic_v2m0>;
0559
0560 bus-range = <0 0xff>;
0561 /* non-prefetchable memory */
0562 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
0563 interrupt-map-mask = <0 0 0 0>;
0564 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
0565 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
0566
0567 num-lanes = <1>;
0568 clock-names = "core", "reg";
0569 clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
0570 status = "disabled";
0571 };
0572
0573 CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
0574 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
0575 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
0576 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
0577 reg-names = "ctrl", "config";
0578 #address-cells = <3>;
0579 #size-cells = <2>;
0580 #interrupt-cells = <1>;
0581 device_type = "pci";
0582 dma-coherent;
0583 msi-parent = <&gic_v2m0>;
0584
0585 bus-range = <0 0xff>;
0586 /* non-prefetchable memory */
0587 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
0588 interrupt-map-mask = <0 0 0 0>;
0589 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
0590 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
0591
0592 num-lanes = <1>;
0593 clock-names = "core", "reg";
0594 clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
0595 status = "disabled";
0596 };
0597 };
