0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2016 Marvell Technology Group Ltd.
0004 *
0005 * Device Tree file for Marvell Armada AP806.
0006 */
0007
0008 #include "armada-ap806.dtsi"
0009
0010 / {
0011 model = "Marvell Armada AP806 Quad";
0012 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
0013
0014 cpus {
0015 #address-cells = <1>;
0016 #size-cells = <0>;
0017
0018 cpu0: cpu@0 {
0019 device_type = "cpu";
0020 compatible = "arm,cortex-a72";
0021 reg = <0x000>;
0022 enable-method = "psci";
0023 #cooling-cells = <2>;
0024 clocks = <&cpu_clk 0>;
0025 i-cache-size = <0xc000>;
0026 i-cache-line-size = <64>;
0027 i-cache-sets = <256>;
0028 d-cache-size = <0x8000>;
0029 d-cache-line-size = <64>;
0030 d-cache-sets = <256>;
0031 next-level-cache = <&l2_0>;
0032 };
0033 cpu1: cpu@1 {
0034 device_type = "cpu";
0035 compatible = "arm,cortex-a72";
0036 reg = <0x001>;
0037 enable-method = "psci";
0038 #cooling-cells = <2>;
0039 clocks = <&cpu_clk 0>;
0040 i-cache-size = <0xc000>;
0041 i-cache-line-size = <64>;
0042 i-cache-sets = <256>;
0043 d-cache-size = <0x8000>;
0044 d-cache-line-size = <64>;
0045 d-cache-sets = <256>;
0046 next-level-cache = <&l2_0>;
0047 };
0048 cpu2: cpu@100 {
0049 device_type = "cpu";
0050 compatible = "arm,cortex-a72";
0051 reg = <0x100>;
0052 enable-method = "psci";
0053 #cooling-cells = <2>;
0054 clocks = <&cpu_clk 1>;
0055 i-cache-size = <0xc000>;
0056 i-cache-line-size = <64>;
0057 i-cache-sets = <256>;
0058 d-cache-size = <0x8000>;
0059 d-cache-line-size = <64>;
0060 d-cache-sets = <256>;
0061 next-level-cache = <&l2_1>;
0062 };
0063 cpu3: cpu@101 {
0064 device_type = "cpu";
0065 compatible = "arm,cortex-a72";
0066 reg = <0x101>;
0067 enable-method = "psci";
0068 #cooling-cells = <2>;
0069 clocks = <&cpu_clk 1>;
0070 i-cache-size = <0xc000>;
0071 i-cache-line-size = <64>;
0072 i-cache-sets = <256>;
0073 d-cache-size = <0x8000>;
0074 d-cache-line-size = <64>;
0075 d-cache-sets = <256>;
0076 next-level-cache = <&l2_1>;
0077 };
0078
0079 l2_0: l2-cache0 {
0080 compatible = "cache";
0081 cache-size = <0x80000>;
0082 cache-line-size = <64>;
0083 cache-sets = <512>;
0084 };
0085
0086 l2_1: l2-cache1 {
0087 compatible = "cache";
0088 cache-size = <0x80000>;
0089 cache-line-size = <64>;
0090 cache-sets = <512>;
0091 };
0092 };
0093 };
