arm64/marvell/armada-80x0.dtsi

0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003  * Copyright (C) 2017 Marvell Technology Group Ltd.
0004  *
0005  * Device Tree file for the Armada 80x0 SoC family
0006  */
0007
0008 / {
0009         aliases {
0010                 gpio1 = &cp1_gpio1;
0011                 gpio2 = &cp0_gpio2;
0012                 spi1 = &cp0_spi0;
0013                 spi2 = &cp0_spi1;
0014                 spi3 = &cp1_spi0;
0015                 spi4 = &cp1_spi1;
0016         };
0017 };
0018
0019 /*
0020  * Instantiate the master CP110
0021  */
0022 #define CP11X_NAME              cp0
0023 #define CP11X_BASE              f2000000
0024 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
0025 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
0026 #define CP11X_PCIE0_BASE        f2600000
0027 #define CP11X_PCIE1_BASE        f2620000
0028 #define CP11X_PCIE2_BASE        f2640000
0029
0030 #include "armada-cp110.dtsi"
0031
0032 #undef CP11X_NAME
0033 #undef CP11X_BASE
0034 #undef CP11X_PCIEx_MEM_BASE
0035 #undef CP11X_PCIEx_MEM_SIZE
0036 #undef CP11X_PCIE0_BASE
0037 #undef CP11X_PCIE1_BASE
0038 #undef CP11X_PCIE2_BASE
0039
0040 /*
0041  * Instantiate the slave CP110
0042  */
0043 #define CP11X_NAME              cp1
0044 #define CP11X_BASE              f4000000
0045 #define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
0046 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
0047 #define CP11X_PCIE0_BASE        f4600000
0048 #define CP11X_PCIE1_BASE        f4620000
0049 #define CP11X_PCIE2_BASE        f4640000
0050
0051 #include "armada-cp110.dtsi"
0052
0053 #undef CP11X_NAME
0054 #undef CP11X_BASE
0055 #undef CP11X_PCIEx_MEM_BASE
0056 #undef CP11X_PCIEx_MEM_SIZE
0057 #undef CP11X_PCIE0_BASE
0058 #undef CP11X_PCIE1_BASE
0059 #undef CP11X_PCIE2_BASE
0060
0061 /* The 80x0 has two CP blocks, but uses only one block from each. */
0062 &cp1_gpio1 {
0063         status = "okay";
0064 };
0065
0066 &cp0_gpio2 {
0067         status = "okay";
0068 };
0069
0070 &cp0_syscon0 {
0071         cp0_pinctrl: pinctrl {
0072                 compatible = "marvell,armada-8k-cpm-pinctrl";
0073         };
0074 };
0075
0076 &cp1_syscon0 {
0077         cp1_pinctrl: pinctrl {
0078                 compatible = "marvell,armada-8k-cps-pinctrl";
0079
0080                 nand_pins: nand-pins {
0081                         marvell,pins =
0082                         "mpp0", "mpp1", "mpp2", "mpp3",
0083                         "mpp4", "mpp5", "mpp6", "mpp7",
0084                         "mpp8", "mpp9", "mpp10", "mpp11",
0085                         "mpp15", "mpp16", "mpp17", "mpp18",
0086                         "mpp19", "mpp20", "mpp21", "mpp22",
0087                         "mpp23", "mpp24", "mpp25", "mpp26",
0088                         "mpp27";
0089                         marvell,function = "dev";
0090                 };
0091
0092                 nand_rb: nand-rb {
0093                         marvell,pins = "mpp13", "mpp12";
0094                         marvell,function = "nf";
0095                 };
0096         };
0097 };
0098
0099 &cp1_crypto {
0100         /*
0101          * The cryptographic engine found on the cp110
0102          * master is enabled by default at the SoC
0103          * level. Because it is not possible as of now
0104          * to enable two cryptographic engines in
0105          * parallel, disable this one by default.
0106          */
0107         status = "disabled";
0108 };