0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2016 Marvell Technology Group Ltd.
0004 *
0005 * Device Tree file for MACCHIATOBin Armada 8040 community board platform
0006 */
0007
0008 #include "armada-8040.dtsi"
0009
0010 #include <dt-bindings/gpio/gpio.h>
0011
0012 / {
0013 model = "Marvell 8040 MACCHIATOBin";
0014 compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
0015 "marvell,armada-ap806-quad", "marvell,armada-ap806";
0016
0017 chosen {
0018 stdout-path = "serial0:115200n8";
0019 };
0020
0021 memory@0 {
0022 device_type = "memory";
0023 reg = <0x0 0x0 0x0 0x80000000>;
0024 };
0025
0026 aliases {
0027 ethernet0 = &cp0_eth0;
0028 ethernet1 = &cp1_eth0;
0029 ethernet2 = &cp1_eth1;
0030 ethernet3 = &cp1_eth2;
0031 };
0032
0033 /* Regulator labels correspond with schematics */
0034 v_3_3: regulator-3-3v {
0035 compatible = "regulator-fixed";
0036 regulator-name = "v_3_3";
0037 regulator-min-microvolt = <3300000>;
0038 regulator-max-microvolt = <3300000>;
0039 regulator-always-on;
0040 status = "okay";
0041 };
0042
0043 v_vddo_h: regulator-1-8v {
0044 compatible = "regulator-fixed";
0045 regulator-name = "v_vddo_h";
0046 regulator-min-microvolt = <1800000>;
0047 regulator-max-microvolt = <1800000>;
0048 regulator-always-on;
0049 status = "okay";
0050 };
0051
0052 v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
0053 compatible = "regulator-fixed";
0054 enable-active-high;
0055 gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
0056 pinctrl-names = "default";
0057 pinctrl-0 = <&cp0_xhci_vbus_pins>;
0058 regulator-name = "v_5v0_usb3_hst_vbus";
0059 regulator-min-microvolt = <5000000>;
0060 regulator-max-microvolt = <5000000>;
0061 status = "okay";
0062 };
0063
0064 sfp_eth0: sfp-eth0 {
0065 /* CON15,16 - CPM lane 4 */
0066 compatible = "sff,sfp";
0067 i2c-bus = <&sfpp0_i2c>;
0068 los-gpios = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
0069 mod-def0-gpios = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
0070 tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
0071 tx-fault-gpios = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
0072 pinctrl-names = "default";
0073 pinctrl-0 = <&cp1_sfpp0_pins>;
0074 maximum-power-milliwatt = <2000>;
0075 };
0076
0077 sfp_eth1: sfp-eth1 {
0078 /* CON17,18 - CPS lane 4 */
0079 compatible = "sff,sfp";
0080 i2c-bus = <&sfpp1_i2c>;
0081 los-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
0082 mod-def0-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
0083 tx-disable-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
0084 tx-fault-gpios = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
0085 pinctrl-names = "default";
0086 pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
0087 maximum-power-milliwatt = <2000>;
0088 };
0089
0090 sfp_eth3: sfp-eth3 {
0091 /* CON13,14 - CPS lane 5 */
0092 compatible = "sff,sfp";
0093 i2c-bus = <&sfp_1g_i2c>;
0094 los-gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
0095 mod-def0-gpios = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
0096 tx-disable-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
0097 tx-fault-gpios = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
0098 pinctrl-names = "default";
0099 pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
0100 maximum-power-milliwatt = <2000>;
0101 };
0102 };
0103
0104 &uart0 {
0105 status = "okay";
0106 pinctrl-0 = <&uart0_pins>;
0107 pinctrl-names = "default";
0108 };
0109
0110 &ap_sdhci0 {
0111 bus-width = <8>;
0112 /*
0113 * Not stable in HS modes - phy needs "more calibration", so add
0114 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
0115 */
0116 marvell,xenon-phy-slow-mode;
0117 no-1-8-v;
0118 no-sd;
0119 no-sdio;
0120 non-removable;
0121 status = "okay";
0122 vqmmc-supply = <&v_vddo_h>;
0123 };
0124
0125 &cp0_i2c0 {
0126 clock-frequency = <100000>;
0127 pinctrl-names = "default";
0128 pinctrl-0 = <&cp0_i2c0_pins>;
0129 status = "okay";
0130 };
0131
0132 &cp0_i2c1 {
0133 clock-frequency = <100000>;
0134 pinctrl-names = "default";
0135 pinctrl-0 = <&cp0_i2c1_pins>;
0136 status = "okay";
0137
0138 i2c-switch@70 {
0139 compatible = "nxp,pca9548";
0140 #address-cells = <1>;
0141 #size-cells = <0>;
0142 reg = <0x70>;
0143
0144 sfpp0_i2c: i2c@0 {
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 reg = <0>;
0148 };
0149 sfpp1_i2c: i2c@1 {
0150 #address-cells = <1>;
0151 #size-cells = <0>;
0152 reg = <1>;
0153 };
0154 sfp_1g_i2c: i2c@2 {
0155 #address-cells = <1>;
0156 #size-cells = <0>;
0157 reg = <2>;
0158 };
0159 };
0160 };
0161
0162 /* J25 UART header */
0163 &cp0_uart1 {
0164 pinctrl-names = "default";
0165 pinctrl-0 = <&cp0_uart1_pins>;
0166 status = "okay";
0167 };
0168
0169 &cp0_mdio {
0170 pinctrl-names = "default";
0171 pinctrl-0 = <&cp0_ge_mdio_pins>;
0172 status = "okay";
0173
0174 ge_phy: ethernet-phy@0 {
0175 reg = <0>;
0176 };
0177 };
0178
0179 &cp0_pcie0 {
0180 pinctrl-names = "default";
0181 pinctrl-0 = <&cp0_pcie_pins>;
0182 num-lanes = <4>;
0183 num-viewport = <8>;
0184 reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
0185 ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
0186 phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
0187 <&cp0_comphy2 0>, <&cp0_comphy3 0>;
0188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
0189 "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
0190 status = "okay";
0191 };
0192
0193 &cp0_pinctrl {
0194 cp0_ge_mdio_pins: ge-mdio-pins {
0195 marvell,pins = "mpp32", "mpp34";
0196 marvell,function = "ge";
0197 };
0198 cp0_i2c1_pins: i2c1-pins {
0199 marvell,pins = "mpp35", "mpp36";
0200 marvell,function = "i2c1";
0201 };
0202 cp0_i2c0_pins: i2c0-pins {
0203 marvell,pins = "mpp37", "mpp38";
0204 marvell,function = "i2c0";
0205 };
0206 cp0_uart1_pins: uart1-pins {
0207 marvell,pins = "mpp40", "mpp41";
0208 marvell,function = "uart1";
0209 };
0210 cp0_xhci_vbus_pins: xhci0-vbus-pins {
0211 marvell,pins = "mpp47";
0212 marvell,function = "gpio";
0213 };
0214 cp0_sfp_1g_pins: sfp-1g-pins {
0215 marvell,pins = "mpp51", "mpp53", "mpp54";
0216 marvell,function = "gpio";
0217 };
0218 cp0_pcie_pins: pcie-pins {
0219 marvell,pins = "mpp52";
0220 marvell,function = "gpio";
0221 };
0222 cp0_sdhci_pins: sdhci-pins {
0223 marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
0224 "mpp60", "mpp61";
0225 marvell,function = "sdio";
0226 };
0227 cp0_sfpp1_pins: sfpp1-pins {
0228 marvell,pins = "mpp62";
0229 marvell,function = "gpio";
0230 };
0231 };
0232
0233 &cp0_ethernet {
0234 status = "okay";
0235 };
0236
0237 &cp0_eth0 {
0238 /* Generic PHY, providing serdes lanes */
0239 phys = <&cp0_comphy4 0>;
0240 };
0241
0242 &cp0_sata0 {
0243 status = "okay";
0244
0245 /* CPM Lane 5 - U29 */
0246 sata-port@1 {
0247 phys = <&cp0_comphy5 1>;
0248 phy-names = "cp0-sata0-1-phy";
0249 };
0250 };
0251
0252 &cp0_sdhci0 {
0253 /* U6 */
0254 broken-cd;
0255 bus-width = <4>;
0256 pinctrl-names = "default";
0257 pinctrl-0 = <&cp0_sdhci_pins>;
0258 status = "okay";
0259 vqmmc-supply = <&v_3_3>;
0260 };
0261
0262 &cp0_utmi {
0263 status = "okay";
0264 };
0265
0266 &cp0_usb3_0 {
0267 /* J38? - USB2.0 only */
0268 phys = <&cp0_utmi0>;
0269 phy-names = "utmi";
0270 dr_mode = "host";
0271 status = "okay";
0272 };
0273
0274 &cp0_usb3_1 {
0275 /* J38? - USB2.0 only */
0276 phys = <&cp0_utmi1>;
0277 phy-names = "utmi";
0278 dr_mode = "host";
0279 status = "okay";
0280 };
0281
0282 &cp1_ethernet {
0283 status = "okay";
0284 };
0285
0286 &cp1_eth0 {
0287 /* Generic PHY, providing serdes lanes */
0288 phys = <&cp1_comphy4 0>;
0289 };
0290
0291 &cp1_eth1 {
0292 /* CPS Lane 0 - J5 (Gigabit RJ45) */
0293 status = "okay";
0294 /* Network PHY */
0295 phy = <&ge_phy>;
0296 phy-mode = "sgmii";
0297 /* Generic PHY, providing serdes lanes */
0298 phys = <&cp1_comphy0 1>;
0299 };
0300
0301 &cp1_eth2 {
0302 /* CPS Lane 5 */
0303 status = "okay";
0304 /* Network PHY */
0305 phy-mode = "2500base-x";
0306 managed = "in-band-status";
0307 /* Generic PHY, providing serdes lanes */
0308 phys = <&cp1_comphy5 2>;
0309 sfp = <&sfp_eth3>;
0310 };
0311
0312 &cp1_pinctrl {
0313 cp1_sfpp1_pins: sfpp1-pins {
0314 marvell,pins = "mpp8", "mpp10", "mpp11";
0315 marvell,function = "gpio";
0316 };
0317 cp1_spi1_pins: spi1-pins {
0318 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
0319 marvell,function = "spi1";
0320 };
0321 cp1_uart0_pins: uart0-pins {
0322 marvell,pins = "mpp6", "mpp7";
0323 marvell,function = "uart0";
0324 };
0325 cp1_sfp_1g_pins: sfp-1g-pins {
0326 marvell,pins = "mpp24";
0327 marvell,function = "gpio";
0328 };
0329 cp1_sfpp0_pins: sfpp0-pins {
0330 marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
0331 marvell,function = "gpio";
0332 };
0333 };
0334
0335 /* J27 UART header */
0336 &cp1_uart0 {
0337 pinctrl-names = "default";
0338 pinctrl-0 = <&cp1_uart0_pins>;
0339 status = "okay";
0340 };
0341
0342 &cp1_sata0 {
0343 status = "okay";
0344
0345 /* CPS Lane 1 - U32 */
0346 sata-port@0 {
0347 phys = <&cp1_comphy1 0>;
0348 phy-names = "cp1-sata0-0-phy";
0349 };
0350
0351 /* CPS Lane 3 - U31 */
0352 sata-port@1 {
0353 phys = <&cp1_comphy3 1>;
0354 phy-names = "cp1-sata0-1-phy";
0355 };
0356 };
0357
0358 &cp1_spi1 {
0359 pinctrl-names = "default";
0360 pinctrl-0 = <&cp1_spi1_pins>;
0361 status = "okay";
0362
0363 flash@0 {
0364 compatible = "st,w25q32";
0365 spi-max-frequency = <50000000>;
0366 reg = <0>;
0367 };
0368 };
0369
0370 &cp1_comphy2 {
0371 cp1_usbh0_con: connector {
0372 compatible = "usb-a-connector";
0373 phy-supply = <&v_5v0_usb3_hst_vbus>;
0374 };
0375 };
0376
0377 &cp1_utmi {
0378 status = "okay";
0379 };
0380
0381 &cp1_usb3_0 {
0382 /* CPS Lane 2 - CON7 */
0383 phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
0384 phy-names = "cp1-usb3h0-comphy", "utmi";
0385 dr_mode = "host";
0386 status = "okay";
0387 };
