0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2017 Marvell Technology Group Ltd.
0004 *
0005 * Device Tree file for the Armada 70x0 SoC
0006 */
0007
0008 / {
0009 aliases {
0010 gpio1 = &cp0_gpio1;
0011 gpio2 = &cp0_gpio2;
0012 spi1 = &cp0_spi0;
0013 spi2 = &cp0_spi1;
0014 };
0015 };
0016
0017 /*
0018 * Instantiate the CP110
0019 */
0020 #define CP11X_NAME cp0
0021 #define CP11X_BASE f2000000
0022 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
0023 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
0024 #define CP11X_PCIE0_BASE f2600000
0025 #define CP11X_PCIE1_BASE f2620000
0026 #define CP11X_PCIE2_BASE f2640000
0027
0028 #include "armada-cp110.dtsi"
0029
0030 #undef CP11X_NAME
0031 #undef CP11X_BASE
0032 #undef CP11X_PCIEx_MEM_BASE
0033 #undef CP11X_PCIEx_MEM_SIZE
0034 #undef CP11X_PCIE0_BASE
0035 #undef CP11X_PCIE1_BASE
0036 #undef CP11X_PCIE2_BASE
0037
0038 &cp0_gpio1 {
0039 status = "okay";
0040 };
0041
0042 &cp0_gpio2 {
0043 status = "okay";
0044 };
0045
0046 &cp0_syscon0 {
0047 cp0_pinctrl: pinctrl {
0048 compatible = "marvell,armada-7k-pinctrl";
0049
0050 nand_pins: nand-pins {
0051 marvell,pins =
0052 "mpp15", "mpp16", "mpp17", "mpp18",
0053 "mpp19", "mpp20", "mpp21", "mpp22",
0054 "mpp23", "mpp24", "mpp25", "mpp26",
0055 "mpp27";
0056 marvell,function = "dev";
0057 };
0058
0059 nand_rb: nand-rb {
0060 marvell,pins = "mpp13";
0061 marvell,function = "nf";
0062 };
0063 };
0064 };
