0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (C) 2016 Marvell Technology Group Ltd.
0004 *
0005 * Device Tree file for Marvell Armada 7040 Development board platform
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include "armada-7040.dtsi"
0010
0011 / {
0012 model = "Marvell Armada 7040 DB board";
0013 compatible = "marvell,armada7040-db", "marvell,armada7040",
0014 "marvell,armada-ap806-quad", "marvell,armada-ap806";
0015
0016 chosen {
0017 stdout-path = "serial0:115200n8";
0018 };
0019
0020 memory@0 {
0021 device_type = "memory";
0022 reg = <0x0 0x0 0x0 0x80000000>;
0023 };
0024
0025 aliases {
0026 ethernet0 = &cp0_eth0;
0027 ethernet1 = &cp0_eth1;
0028 ethernet2 = &cp0_eth2;
0029 };
0030
0031 cp0_exp_usb3_0_current_regulator: gpio-regulator {
0032 compatible = "regulator-gpio";
0033 regulator-name = "cp0-usb3-0-current-regulator";
0034 regulator-type = "current";
0035 regulator-min-microamp = <500000>;
0036 regulator-max-microamp = <900000>;
0037 gpios = <&expander0 4 GPIO_ACTIVE_HIGH>;
0038 states = <500000 0x0
0039 900000 0x1>;
0040 enable-active-high;
0041 gpios-states = <0>;
0042 };
0043
0044 cp0_exp_usb3_1_current_regulator: gpio-regulator {
0045 compatible = "regulator-gpio";
0046 regulator-name = "cp0-usb3-1-current-regulator";
0047 regulator-type = "current";
0048 regulator-min-microamp = <500000>;
0049 regulator-max-microamp = <900000>;
0050 gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
0051 states = <500000 0x0
0052 900000 0x1>;
0053 enable-active-high;
0054 gpios-states = <0>;
0055 };
0056
0057 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
0058 compatible = "regulator-fixed";
0059 regulator-name = "usb3h0-vbus";
0060 regulator-min-microvolt = <5000000>;
0061 regulator-max-microvolt = <5000000>;
0062 enable-active-high;
0063 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
0064 vin-supply = <&cp0_exp_usb3_0_current_regulator>;
0065 };
0066
0067 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
0068 compatible = "regulator-fixed";
0069 regulator-name = "usb3h1-vbus";
0070 regulator-min-microvolt = <5000000>;
0071 regulator-max-microvolt = <5000000>;
0072 enable-active-high;
0073 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
0074 vin-supply = <&cp0_exp_usb3_1_current_regulator>;
0075 };
0076 };
0077
0078 &i2c0 {
0079 status = "okay";
0080 clock-frequency = <100000>;
0081 };
0082
0083 &spi0 {
0084 status = "okay";
0085
0086 flash@0 {
0087 compatible = "jedec,spi-nor";
0088 reg = <0>;
0089 spi-max-frequency = <10000000>;
0090
0091 partitions {
0092 compatible = "fixed-partitions";
0093 #address-cells = <1>;
0094 #size-cells = <1>;
0095
0096 partition@0 {
0097 label = "U-Boot";
0098 reg = <0 0x200000>;
0099 };
0100 partition@400000 {
0101 label = "Filesystem";
0102 reg = <0x200000 0xce0000>;
0103 };
0104 };
0105 };
0106 };
0107
0108 &uart0 {
0109 status = "okay";
0110 pinctrl-0 = <&uart0_pins>;
0111 pinctrl-names = "default";
0112 };
0113
0114
0115 &cp0_pcie2 {
0116 status = "okay";
0117 phys = <&cp0_comphy5 2>;
0118 phy-names = "cp0-pcie2-x1-phy";
0119 };
0120
0121 &cp0_i2c0 {
0122 status = "okay";
0123 clock-frequency = <100000>;
0124
0125 expander0: pca9555@21 {
0126 compatible = "nxp,pca9555";
0127 pinctrl-names = "default";
0128 gpio-controller;
0129 #gpio-cells = <2>;
0130 reg = <0x21>;
0131 /*
0132 * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
0133 * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
0134 * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
0135 * IO0_3: USB2_DEVICE_DETECT
0136 * IO0_4: GPIO_0 IO1_4: SD_Status
0137 * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
0138 * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
0139 * IO0_7: IO1_7: SDIO_Vcntrl
0140 */
0141 };
0142 };
0143
0144 &cp0_nand_controller {
0145 /*
0146 * SPI on CPM and NAND have common pins on this board. We can
0147 * use only one at a time. To enable the NAND (which will
0148 * disable the SPI), the "status = "okay";" line have to be
0149 * added here.
0150 */
0151 pinctrl-0 = <&nand_pins>, <&nand_rb>;
0152 pinctrl-names = "default";
0153
0154 nand@0 {
0155 reg = <0>;
0156 label = "pxa3xx_nand-0";
0157 nand-rb = <0>;
0158 nand-on-flash-bbt;
0159 nand-ecc-strength = <4>;
0160 nand-ecc-step-size = <512>;
0161
0162 partitions {
0163 compatible = "fixed-partitions";
0164 #address-cells = <1>;
0165 #size-cells = <1>;
0166
0167 partition@0 {
0168 label = "U-Boot";
0169 reg = <0 0x200000>;
0170 };
0171
0172 partition@200000 {
0173 label = "Linux";
0174 reg = <0x200000 0xe00000>;
0175 };
0176
0177 partition@1000000 {
0178 label = "Filesystem";
0179 reg = <0x1000000 0x3f000000>;
0180 };
0181
0182 };
0183 };
0184 };
0185
0186 &cp0_spi1 {
0187 status = "okay";
0188
0189 flash@0 {
0190 compatible = "jedec,spi-nor";
0191 reg = <0x0>;
0192 spi-max-frequency = <20000000>;
0193
0194 partitions {
0195 compatible = "fixed-partitions";
0196 #address-cells = <1>;
0197 #size-cells = <1>;
0198
0199 partition@0 {
0200 label = "U-Boot";
0201 reg = <0x0 0x200000>;
0202 };
0203
0204 partition@400000 {
0205 label = "Filesystem";
0206 reg = <0x200000 0xe00000>;
0207 };
0208 };
0209 };
0210 };
0211
0212 &cp0_sata0 {
0213 status = "okay";
0214
0215 sata-port@1 {
0216 phys = <&cp0_comphy3 1>;
0217 phy-names = "cp0-sata0-1-phy";
0218 };
0219 };
0220
0221 &cp0_utmi {
0222 status = "okay";
0223 };
0224
0225 &cp0_comphy1 {
0226 cp0_usbh0_con: connector {
0227 compatible = "usb-a-connector";
0228 phy-supply = <&cp0_reg_usb3_0_vbus>;
0229 };
0230 };
0231
0232 &cp0_usb3_0 {
0233 phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
0234 phy-names = "cp0-usb3h0-comphy", "utmi";
0235 dr_mode = "host";
0236 status = "okay";
0237 };
0238
0239 &cp0_comphy4 {
0240 cp0_usbh1_con: connector {
0241 compatible = "usb-a-connector";
0242 phy-supply = <&cp0_reg_usb3_1_vbus>;
0243 };
0244 };
0245
0246 &cp0_usb3_1 {
0247 phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
0248 phy-names = "cp0-usb3h1-comphy", "utmi";
0249 dr_mode = "host";
0250 status = "okay";
0251 };
0252
0253 &ap_sdhci0 {
0254 status = "okay";
0255 bus-width = <4>;
0256 no-1-8-v;
0257 non-removable;
0258 };
0259
0260 &cp0_sdhci0 {
0261 status = "okay";
0262 bus-width = <4>;
0263 no-1-8-v;
0264 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
0265 };
0266
0267 &cp0_mdio {
0268 status = "okay";
0269
0270 phy0: ethernet-phy@0 {
0271 reg = <0>;
0272 };
0273 phy1: ethernet-phy@1 {
0274 reg = <1>;
0275 };
0276 };
0277
0278 &cp0_ethernet {
0279 status = "okay";
0280 };
0281
0282 &cp0_eth0 {
0283 status = "okay";
0284 /* Network PHY */
0285 phy-mode = "10gbase-r";
0286 /* Generic PHY, providing serdes lanes */
0287 phys = <&cp0_comphy2 0>;
0288
0289 fixed-link {
0290 speed = <10000>;
0291 full-duplex;
0292 };
0293 };
0294
0295 &cp0_eth1 {
0296 status = "okay";
0297 /* Network PHY */
0298 phy = <&phy0>;
0299 phy-mode = "sgmii";
0300 /* Generic PHY, providing serdes lanes */
0301 phys = <&cp0_comphy0 1>;
0302 };
0303
0304 &cp0_eth2 {
0305 status = "okay";
0306 phy = <&phy1>;
0307 phy-mode = "rgmii-id";
0308 };
