0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree file for CZ.NIC Turris Mox Board
0004 * 2019 by Marek BehĂșn <kabel@kernel.org>
0005 */
0006
0007 /dts-v1/;
0008
0009 #include <dt-bindings/bus/moxtet.h>
0010 #include <dt-bindings/gpio/gpio.h>
0011 #include <dt-bindings/input/input.h>
0012 #include "armada-372x.dtsi"
0013
0014 / {
0015 model = "CZ.NIC Turris Mox Board";
0016 compatible = "cznic,turris-mox", "marvell,armada3720",
0017 "marvell,armada3710";
0018
0019 aliases {
0020 spi0 = &spi0;
0021 ethernet0 = ð0;
0022 ethernet1 = ð1;
0023 mmc0 = &sdhci0;
0024 mmc1 = &sdhci1;
0025 };
0026
0027 chosen {
0028 stdout-path = "serial0:115200n8";
0029 };
0030
0031 memory@0 {
0032 device_type = "memory";
0033 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
0034 };
0035
0036 leds {
0037 compatible = "gpio-leds";
0038 led {
0039 label = "mox:red:activity";
0040 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
0041 linux,default-trigger = "default-on";
0042 };
0043 };
0044
0045 gpio-keys {
0046 compatible = "gpio-keys";
0047
0048 key-reset {
0049 label = "reset";
0050 linux,code = <KEY_RESTART>;
0051 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
0052 debounce-interval = <60>;
0053 };
0054 };
0055
0056 exp_usb3_vbus: usb3-vbus {
0057 compatible = "regulator-fixed";
0058 regulator-name = "usb3-vbus";
0059 regulator-min-microvolt = <5000000>;
0060 regulator-max-microvolt = <5000000>;
0061 enable-active-high;
0062 regulator-always-on;
0063 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
0064 };
0065
0066 vsdc_reg: vsdc-reg {
0067 compatible = "regulator-gpio";
0068 regulator-name = "vsdc";
0069 regulator-min-microvolt = <1800000>;
0070 regulator-max-microvolt = <3300000>;
0071 regulator-boot-on;
0072
0073 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
0074 gpios-states = <0>;
0075 states = <1800000 0x1
0076 3300000 0x0>;
0077 enable-active-high;
0078 };
0079
0080 vsdio_reg: vsdio-reg {
0081 compatible = "regulator-gpio";
0082 regulator-name = "vsdio";
0083 regulator-min-microvolt = <1800000>;
0084 regulator-max-microvolt = <3300000>;
0085 regulator-boot-on;
0086
0087 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
0088 gpios-states = <0>;
0089 states = <1800000 0x1
0090 3300000 0x0>;
0091 enable-active-high;
0092 };
0093
0094 sdhci1_pwrseq: sdhci1-pwrseq {
0095 compatible = "mmc-pwrseq-simple";
0096 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
0097 status = "okay";
0098 };
0099
0100 sfp: sfp {
0101 compatible = "sff,sfp";
0102 i2c-bus = <&i2c0>;
0103 los-gpios = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
0104 tx-fault-gpios = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
0105 mod-def0-gpios = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
0106 tx-disable-gpios = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
0107 rate-select0-gpios = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
0108 maximum-power-milliwatt = <3000>;
0109
0110 /* enabled by U-Boot if SFP module is present */
0111 status = "disabled";
0112 };
0113
0114 firmware {
0115 armada-3700-rwtm {
0116 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
0117 };
0118 };
0119 };
0120
0121 &i2c0 {
0122 pinctrl-names = "default";
0123 pinctrl-0 = <&i2c1_pins>;
0124 clock-frequency = <100000>;
0125 /delete-property/ mrvl,i2c-fast-mode;
0126 status = "okay";
0127
0128 rtc@6f {
0129 compatible = "microchip,mcp7940x";
0130 reg = <0x6f>;
0131 };
0132 };
0133
0134 &pcie0 {
0135 pinctrl-names = "default";
0136 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
0137 status = "okay";
0138 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
0139 /*
0140 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
0141 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
0142 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
0143 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
0144 * no remapping) and that this address is the lowest from all specified ranges. If these
0145 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
0146 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
0147 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
0148 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
0149 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
0150 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
0151 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
0152 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
0153 * Bug related to requirement of same child and parent addresses for first range is fixed
0154 * in U-Boot version 2022.04 by following commit:
0155 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
0156 */
0157 #address-cells = <3>;
0158 #size-cells = <2>;
0159 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
0160 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
0161
0162 /* enabled by U-Boot if PCIe module is present */
0163 status = "disabled";
0164 };
0165
0166 &uart0 {
0167 status = "okay";
0168 };
0169
0170 ð0 {
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&rgmii_pins>;
0173 phy-mode = "rgmii-id";
0174 phy-handle = <&phy1>;
0175 status = "okay";
0176 };
0177
0178 ð1 {
0179 phy-mode = "2500base-x";
0180 managed = "in-band-status";
0181 phys = <&comphy0 1>;
0182 };
0183
0184 &sdhci0 {
0185 wp-inverted;
0186 bus-width = <4>;
0187 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
0188 vqmmc-supply = <&vsdc_reg>;
0189 marvell,pad-type = "sd";
0190 status = "okay";
0191 };
0192
0193 &sdhci1 {
0194 pinctrl-names = "default";
0195 pinctrl-0 = <&sdio_pins>;
0196 non-removable;
0197 bus-width = <4>;
0198 marvell,pad-type = "sd";
0199 vqmmc-supply = <&vsdio_reg>;
0200 mmc-pwrseq = <&sdhci1_pwrseq>;
0201 /* forbid SDR104 for FCC purposes */
0202 sdhci-caps-mask = <0x2 0x0>;
0203 status = "okay";
0204 };
0205
0206 &spi0 {
0207 status = "okay";
0208 pinctrl-names = "default";
0209 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
0210 assigned-clocks = <&nb_periph_clk 7>;
0211 assigned-clock-parents = <&tbg 1>;
0212 assigned-clock-rates = <20000000>;
0213
0214 flash@0 {
0215 #address-cells = <1>;
0216 #size-cells = <1>;
0217 compatible = "jedec,spi-nor";
0218 reg = <0>;
0219 spi-max-frequency = <20000000>;
0220
0221 partitions {
0222 compatible = "fixed-partitions";
0223 #address-cells = <1>;
0224 #size-cells = <1>;
0225
0226 partition@0 {
0227 label = "secure-firmware";
0228 reg = <0x0 0x20000>;
0229 };
0230
0231 partition@20000 {
0232 label = "a53-firmware";
0233 reg = <0x20000 0x160000>;
0234 };
0235
0236 partition@180000 {
0237 label = "u-boot-env";
0238 reg = <0x180000 0x10000>;
0239 };
0240
0241 partition@190000 {
0242 label = "Rescue system";
0243 reg = <0x190000 0x660000>;
0244 };
0245
0246 partition@7f0000 {
0247 label = "dtb";
0248 reg = <0x7f0000 0x10000>;
0249 };
0250 };
0251 };
0252
0253 moxtet: moxtet@1 {
0254 #address-cells = <1>;
0255 #size-cells = <0>;
0256 compatible = "cznic,moxtet";
0257 reg = <1>;
0258 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
0259 spi-max-frequency = <10000000>;
0260 spi-cpol;
0261 spi-cpha;
0262 interrupt-controller;
0263 #interrupt-cells = <1>;
0264 interrupt-parent = <&gpiosb>;
0265 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
0266 status = "okay";
0267
0268 moxtet_sfp: gpio@0 {
0269 compatible = "cznic,moxtet-gpio";
0270 gpio-controller;
0271 #gpio-cells = <2>;
0272 reg = <0>;
0273 status = "disabled";
0274 };
0275 };
0276 };
0277
0278 &usb2 {
0279 status = "okay";
0280 };
0281
0282 &comphy2 {
0283 connector {
0284 compatible = "usb-a-connector";
0285 phy-supply = <&exp_usb3_vbus>;
0286 };
0287 };
0288
0289 &usb3 {
0290 status = "okay";
0291 phys = <&comphy2 0>;
0292 };
0293
0294 &mdio {
0295 pinctrl-names = "default";
0296 pinctrl-0 = <&smi_pins>;
0297 status = "okay";
0298
0299 phy1: ethernet-phy@1 {
0300 reg = <1>;
0301 };
0302
0303 /* switch nodes are enabled by U-Boot if modules are present */
0304 switch0@10 {
0305 compatible = "marvell,mv88e6190";
0306 reg = <0x10>;
0307 dsa,member = <0 0>;
0308 interrupt-parent = <&moxtet>;
0309 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
0310 status = "disabled";
0311
0312 mdio {
0313 #address-cells = <1>;
0314 #size-cells = <0>;
0315
0316 switch0phy1: switch0phy1@1 {
0317 reg = <0x1>;
0318 };
0319
0320 switch0phy2: switch0phy2@2 {
0321 reg = <0x2>;
0322 };
0323
0324 switch0phy3: switch0phy3@3 {
0325 reg = <0x3>;
0326 };
0327
0328 switch0phy4: switch0phy4@4 {
0329 reg = <0x4>;
0330 };
0331
0332 switch0phy5: switch0phy5@5 {
0333 reg = <0x5>;
0334 };
0335
0336 switch0phy6: switch0phy6@6 {
0337 reg = <0x6>;
0338 };
0339
0340 switch0phy7: switch0phy7@7 {
0341 reg = <0x7>;
0342 };
0343
0344 switch0phy8: switch0phy8@8 {
0345 reg = <0x8>;
0346 };
0347 };
0348
0349 ports {
0350 #address-cells = <1>;
0351 #size-cells = <0>;
0352
0353 port@1 {
0354 reg = <0x1>;
0355 label = "lan1";
0356 phy-handle = <&switch0phy1>;
0357 };
0358
0359 port@2 {
0360 reg = <0x2>;
0361 label = "lan2";
0362 phy-handle = <&switch0phy2>;
0363 };
0364
0365 port@3 {
0366 reg = <0x3>;
0367 label = "lan3";
0368 phy-handle = <&switch0phy3>;
0369 };
0370
0371 port@4 {
0372 reg = <0x4>;
0373 label = "lan4";
0374 phy-handle = <&switch0phy4>;
0375 };
0376
0377 port@5 {
0378 reg = <0x5>;
0379 label = "lan5";
0380 phy-handle = <&switch0phy5>;
0381 };
0382
0383 port@6 {
0384 reg = <0x6>;
0385 label = "lan6";
0386 phy-handle = <&switch0phy6>;
0387 };
0388
0389 port@7 {
0390 reg = <0x7>;
0391 label = "lan7";
0392 phy-handle = <&switch0phy7>;
0393 };
0394
0395 port@8 {
0396 reg = <0x8>;
0397 label = "lan8";
0398 phy-handle = <&switch0phy8>;
0399 };
0400
0401 port@9 {
0402 reg = <0x9>;
0403 label = "cpu";
0404 ethernet = <ð1>;
0405 phy-mode = "2500base-x";
0406 managed = "in-band-status";
0407 };
0408
0409 switch0port10: port@a {
0410 reg = <0xa>;
0411 label = "dsa";
0412 phy-mode = "2500base-x";
0413 managed = "in-band-status";
0414 link = <&switch1port9 &switch2port9>;
0415 status = "disabled";
0416 };
0417
0418 port-sfp@a {
0419 reg = <0xa>;
0420 label = "sfp";
0421 sfp = <&sfp>;
0422 phy-mode = "sgmii";
0423 managed = "in-band-status";
0424 status = "disabled";
0425 };
0426 };
0427 };
0428
0429 switch0@2 {
0430 compatible = "marvell,mv88e6085";
0431 reg = <0x2>;
0432 dsa,member = <0 0>;
0433 interrupt-parent = <&moxtet>;
0434 interrupts = <MOXTET_IRQ_TOPAZ>;
0435 status = "disabled";
0436
0437 mdio {
0438 #address-cells = <1>;
0439 #size-cells = <0>;
0440
0441 switch0phy1_topaz: switch0phy1@11 {
0442 reg = <0x11>;
0443 };
0444
0445 switch0phy2_topaz: switch0phy2@12 {
0446 reg = <0x12>;
0447 };
0448
0449 switch0phy3_topaz: switch0phy3@13 {
0450 reg = <0x13>;
0451 };
0452
0453 switch0phy4_topaz: switch0phy4@14 {
0454 reg = <0x14>;
0455 };
0456 };
0457
0458 ports {
0459 #address-cells = <1>;
0460 #size-cells = <0>;
0461
0462 port@1 {
0463 reg = <0x1>;
0464 label = "lan1";
0465 phy-handle = <&switch0phy1_topaz>;
0466 };
0467
0468 port@2 {
0469 reg = <0x2>;
0470 label = "lan2";
0471 phy-handle = <&switch0phy2_topaz>;
0472 };
0473
0474 port@3 {
0475 reg = <0x3>;
0476 label = "lan3";
0477 phy-handle = <&switch0phy3_topaz>;
0478 };
0479
0480 port@4 {
0481 reg = <0x4>;
0482 label = "lan4";
0483 phy-handle = <&switch0phy4_topaz>;
0484 };
0485
0486 port@5 {
0487 reg = <0x5>;
0488 label = "cpu";
0489 phy-mode = "2500base-x";
0490 managed = "in-band-status";
0491 ethernet = <ð1>;
0492 };
0493 };
0494 };
0495
0496 switch1@11 {
0497 compatible = "marvell,mv88e6190";
0498 reg = <0x11>;
0499 dsa,member = <0 1>;
0500 interrupt-parent = <&moxtet>;
0501 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
0502 status = "disabled";
0503
0504 mdio {
0505 #address-cells = <1>;
0506 #size-cells = <0>;
0507
0508 switch1phy1: switch1phy1@1 {
0509 reg = <0x1>;
0510 };
0511
0512 switch1phy2: switch1phy2@2 {
0513 reg = <0x2>;
0514 };
0515
0516 switch1phy3: switch1phy3@3 {
0517 reg = <0x3>;
0518 };
0519
0520 switch1phy4: switch1phy4@4 {
0521 reg = <0x4>;
0522 };
0523
0524 switch1phy5: switch1phy5@5 {
0525 reg = <0x5>;
0526 };
0527
0528 switch1phy6: switch1phy6@6 {
0529 reg = <0x6>;
0530 };
0531
0532 switch1phy7: switch1phy7@7 {
0533 reg = <0x7>;
0534 };
0535
0536 switch1phy8: switch1phy8@8 {
0537 reg = <0x8>;
0538 };
0539 };
0540
0541 ports {
0542 #address-cells = <1>;
0543 #size-cells = <0>;
0544
0545 port@1 {
0546 reg = <0x1>;
0547 label = "lan9";
0548 phy-handle = <&switch1phy1>;
0549 };
0550
0551 port@2 {
0552 reg = <0x2>;
0553 label = "lan10";
0554 phy-handle = <&switch1phy2>;
0555 };
0556
0557 port@3 {
0558 reg = <0x3>;
0559 label = "lan11";
0560 phy-handle = <&switch1phy3>;
0561 };
0562
0563 port@4 {
0564 reg = <0x4>;
0565 label = "lan12";
0566 phy-handle = <&switch1phy4>;
0567 };
0568
0569 port@5 {
0570 reg = <0x5>;
0571 label = "lan13";
0572 phy-handle = <&switch1phy5>;
0573 };
0574
0575 port@6 {
0576 reg = <0x6>;
0577 label = "lan14";
0578 phy-handle = <&switch1phy6>;
0579 };
0580
0581 port@7 {
0582 reg = <0x7>;
0583 label = "lan15";
0584 phy-handle = <&switch1phy7>;
0585 };
0586
0587 port@8 {
0588 reg = <0x8>;
0589 label = "lan16";
0590 phy-handle = <&switch1phy8>;
0591 };
0592
0593 switch1port9: port@9 {
0594 reg = <0x9>;
0595 label = "dsa";
0596 phy-mode = "2500base-x";
0597 managed = "in-band-status";
0598 link = <&switch0port10>;
0599 };
0600
0601 switch1port10: port@a {
0602 reg = <0xa>;
0603 label = "dsa";
0604 phy-mode = "2500base-x";
0605 managed = "in-band-status";
0606 link = <&switch2port9>;
0607 status = "disabled";
0608 };
0609
0610 port-sfp@a {
0611 reg = <0xa>;
0612 label = "sfp";
0613 sfp = <&sfp>;
0614 phy-mode = "sgmii";
0615 managed = "in-band-status";
0616 status = "disabled";
0617 };
0618 };
0619 };
0620
0621 switch1@2 {
0622 compatible = "marvell,mv88e6085";
0623 reg = <0x2>;
0624 dsa,member = <0 1>;
0625 interrupt-parent = <&moxtet>;
0626 interrupts = <MOXTET_IRQ_TOPAZ>;
0627 status = "disabled";
0628
0629 mdio {
0630 #address-cells = <1>;
0631 #size-cells = <0>;
0632
0633 switch1phy1_topaz: switch1phy1@11 {
0634 reg = <0x11>;
0635 };
0636
0637 switch1phy2_topaz: switch1phy2@12 {
0638 reg = <0x12>;
0639 };
0640
0641 switch1phy3_topaz: switch1phy3@13 {
0642 reg = <0x13>;
0643 };
0644
0645 switch1phy4_topaz: switch1phy4@14 {
0646 reg = <0x14>;
0647 };
0648 };
0649
0650 ports {
0651 #address-cells = <1>;
0652 #size-cells = <0>;
0653
0654 port@1 {
0655 reg = <0x1>;
0656 label = "lan9";
0657 phy-handle = <&switch1phy1_topaz>;
0658 };
0659
0660 port@2 {
0661 reg = <0x2>;
0662 label = "lan10";
0663 phy-handle = <&switch1phy2_topaz>;
0664 };
0665
0666 port@3 {
0667 reg = <0x3>;
0668 label = "lan11";
0669 phy-handle = <&switch1phy3_topaz>;
0670 };
0671
0672 port@4 {
0673 reg = <0x4>;
0674 label = "lan12";
0675 phy-handle = <&switch1phy4_topaz>;
0676 };
0677
0678 port@5 {
0679 reg = <0x5>;
0680 label = "dsa";
0681 phy-mode = "2500base-x";
0682 managed = "in-band-status";
0683 link = <&switch0port10>;
0684 };
0685 };
0686 };
0687
0688 switch2@12 {
0689 compatible = "marvell,mv88e6190";
0690 reg = <0x12>;
0691 dsa,member = <0 2>;
0692 interrupt-parent = <&moxtet>;
0693 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
0694 status = "disabled";
0695
0696 mdio {
0697 #address-cells = <1>;
0698 #size-cells = <0>;
0699
0700 switch2phy1: switch2phy1@1 {
0701 reg = <0x1>;
0702 };
0703
0704 switch2phy2: switch2phy2@2 {
0705 reg = <0x2>;
0706 };
0707
0708 switch2phy3: switch2phy3@3 {
0709 reg = <0x3>;
0710 };
0711
0712 switch2phy4: switch2phy4@4 {
0713 reg = <0x4>;
0714 };
0715
0716 switch2phy5: switch2phy5@5 {
0717 reg = <0x5>;
0718 };
0719
0720 switch2phy6: switch2phy6@6 {
0721 reg = <0x6>;
0722 };
0723
0724 switch2phy7: switch2phy7@7 {
0725 reg = <0x7>;
0726 };
0727
0728 switch2phy8: switch2phy8@8 {
0729 reg = <0x8>;
0730 };
0731 };
0732
0733 ports {
0734 #address-cells = <1>;
0735 #size-cells = <0>;
0736
0737 port@1 {
0738 reg = <0x1>;
0739 label = "lan17";
0740 phy-handle = <&switch2phy1>;
0741 };
0742
0743 port@2 {
0744 reg = <0x2>;
0745 label = "lan18";
0746 phy-handle = <&switch2phy2>;
0747 };
0748
0749 port@3 {
0750 reg = <0x3>;
0751 label = "lan19";
0752 phy-handle = <&switch2phy3>;
0753 };
0754
0755 port@4 {
0756 reg = <0x4>;
0757 label = "lan20";
0758 phy-handle = <&switch2phy4>;
0759 };
0760
0761 port@5 {
0762 reg = <0x5>;
0763 label = "lan21";
0764 phy-handle = <&switch2phy5>;
0765 };
0766
0767 port@6 {
0768 reg = <0x6>;
0769 label = "lan22";
0770 phy-handle = <&switch2phy6>;
0771 };
0772
0773 port@7 {
0774 reg = <0x7>;
0775 label = "lan23";
0776 phy-handle = <&switch2phy7>;
0777 };
0778
0779 port@8 {
0780 reg = <0x8>;
0781 label = "lan24";
0782 phy-handle = <&switch2phy8>;
0783 };
0784
0785 switch2port9: port@9 {
0786 reg = <0x9>;
0787 label = "dsa";
0788 phy-mode = "2500base-x";
0789 managed = "in-band-status";
0790 link = <&switch1port10 &switch0port10>;
0791 };
0792
0793 port-sfp@a {
0794 reg = <0xa>;
0795 label = "sfp";
0796 sfp = <&sfp>;
0797 phy-mode = "sgmii";
0798 managed = "in-band-status";
0799 status = "disabled";
0800 };
0801 };
0802 };
0803
0804 switch2@2 {
0805 compatible = "marvell,mv88e6085";
0806 reg = <0x2>;
0807 dsa,member = <0 2>;
0808 interrupt-parent = <&moxtet>;
0809 interrupts = <MOXTET_IRQ_TOPAZ>;
0810 status = "disabled";
0811
0812 mdio {
0813 #address-cells = <1>;
0814 #size-cells = <0>;
0815
0816 switch2phy1_topaz: switch2phy1@11 {
0817 reg = <0x11>;
0818 };
0819
0820 switch2phy2_topaz: switch2phy2@12 {
0821 reg = <0x12>;
0822 };
0823
0824 switch2phy3_topaz: switch2phy3@13 {
0825 reg = <0x13>;
0826 };
0827
0828 switch2phy4_topaz: switch2phy4@14 {
0829 reg = <0x14>;
0830 };
0831 };
0832
0833 ports {
0834 #address-cells = <1>;
0835 #size-cells = <0>;
0836
0837 port@1 {
0838 reg = <0x1>;
0839 label = "lan17";
0840 phy-handle = <&switch2phy1_topaz>;
0841 };
0842
0843 port@2 {
0844 reg = <0x2>;
0845 label = "lan18";
0846 phy-handle = <&switch2phy2_topaz>;
0847 };
0848
0849 port@3 {
0850 reg = <0x3>;
0851 label = "lan19";
0852 phy-handle = <&switch2phy3_topaz>;
0853 };
0854
0855 port@4 {
0856 reg = <0x4>;
0857 label = "lan20";
0858 phy-handle = <&switch2phy4_topaz>;
0859 };
0860
0861 port@5 {
0862 reg = <0x5>;
0863 label = "dsa";
0864 phy-mode = "2500base-x";
0865 managed = "in-band-status";
0866 link = <&switch1port10 &switch0port10>;
0867 };
0868 };
0869 };
0870 };