0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree For AC5.
0004 *
0005 * Copyright (C) 2021 Marvell
0006 * Copyright (C) 2022 Allied Telesis Labs
0007 */
0008
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011
0012 / {
0013 model = "Marvell AC5 SoC";
0014 compatible = "marvell,ac5";
0015 interrupt-parent = <&gic>;
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018
0019 cpus {
0020 #address-cells = <2>;
0021 #size-cells = <0>;
0022
0023 cpu-map {
0024 cluster0 {
0025 core0 {
0026 cpu = <&cpu0>;
0027 };
0028 core1 {
0029 cpu = <&cpu1>;
0030 };
0031 };
0032 };
0033
0034 cpu0: cpu@0 {
0035 device_type = "cpu";
0036 compatible = "arm,cortex-a55";
0037 reg = <0x0 0x0>;
0038 enable-method = "psci";
0039 next-level-cache = <&l2>;
0040 };
0041
0042 cpu1: cpu@1 {
0043 device_type = "cpu";
0044 compatible = "arm,cortex-a55";
0045 reg = <0x0 0x100>;
0046 enable-method = "psci";
0047 next-level-cache = <&l2>;
0048 };
0049
0050 l2: l2-cache {
0051 compatible = "cache";
0052 };
0053 };
0054
0055 psci {
0056 compatible = "arm,psci-0.2";
0057 method = "smc";
0058 };
0059
0060 timer {
0061 compatible = "arm,armv8-timer";
0062 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
0063 <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
0064 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
0065 <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0066 };
0067
0068 pmu {
0069 compatible = "arm,armv8-pmuv3";
0070 interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
0071 };
0072
0073 soc {
0074 compatible = "simple-bus";
0075 #address-cells = <2>;
0076 #size-cells = <2>;
0077 ranges;
0078 dma-ranges;
0079
0080 internal-regs@7f000000 {
0081 #address-cells = <1>;
0082 #size-cells = <1>;
0083 compatible = "simple-bus";
0084 /* 16M internal register @ 0x7f00_0000 */
0085 ranges = <0x0 0x0 0x7f000000 0x1000000>;
0086 dma-coherent;
0087
0088 uart0: serial@12000 {
0089 compatible = "snps,dw-apb-uart";
0090 reg = <0x12000 0x100>;
0091 reg-shift = <2>;
0092 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0093 reg-io-width = <1>;
0094 clocks = <&cnm_clock>;
0095 status = "okay";
0096 };
0097
0098 mdio: mdio@22004 {
0099 #address-cells = <1>;
0100 #size-cells = <0>;
0101 compatible = "marvell,orion-mdio";
0102 reg = <0x22004 0x4>;
0103 clocks = <&cnm_clock>;
0104 };
0105
0106 i2c0: i2c@11000{
0107 compatible = "marvell,mv78230-i2c";
0108 reg = <0x11000 0x20>;
0109 #address-cells = <1>;
0110 #size-cells = <0>;
0111
0112 clocks = <&cnm_clock>;
0113 clock-names = "core";
0114 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0115 clock-frequency=<100000>;
0116
0117 pinctrl-names = "default", "gpio";
0118 pinctrl-0 = <&i2c0_pins>;
0119 pinctrl-1 = <&i2c0_gpio>;
0120 scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
0121 sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
0122 status = "disabled";
0123 };
0124
0125 i2c1: i2c@11100{
0126 compatible = "marvell,mv78230-i2c";
0127 reg = <0x11100 0x20>;
0128 #address-cells = <1>;
0129 #size-cells = <0>;
0130
0131 clocks = <&cnm_clock>;
0132 clock-names = "core";
0133 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0134 clock-frequency=<100000>;
0135
0136 pinctrl-names = "default", "gpio";
0137 pinctrl-0 = <&i2c1_pins>;
0138 pinctrl-1 = <&i2c1_gpio>;
0139 scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
0140 sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
0141 status = "disabled";
0142 };
0143
0144 gpio0: gpio@18100 {
0145 compatible = "marvell,orion-gpio";
0146 reg = <0x18100 0x40>;
0147 ngpios = <32>;
0148 gpio-controller;
0149 #gpio-cells = <2>;
0150 gpio-ranges = <&pinctrl0 0 0 32>;
0151 marvell,pwm-offset = <0x1f0>;
0152 interrupt-controller;
0153 #interrupt-cells = <2>;
0154 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
0157 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0158 };
0159
0160 gpio1: gpio@18140 {
0161 reg = <0x18140 0x40>;
0162 compatible = "marvell,orion-gpio";
0163 ngpios = <14>;
0164 gpio-controller;
0165 #gpio-cells = <2>;
0166 gpio-ranges = <&pinctrl0 0 32 14>;
0167 marvell,pwm-offset = <0x1f0>;
0168 interrupt-controller;
0169 #interrupt-cells = <2>;
0170 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
0171 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0172 };
0173 };
0174
0175 /*
0176 * Dedicated section for devices behind 32bit controllers so we
0177 * can configure specific DMA mapping for them
0178 */
0179 behind-32bit-controller@7f000000 {
0180 compatible = "simple-bus";
0181 #address-cells = <0x2>;
0182 #size-cells = <0x2>;
0183 ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
0184 /* Host phy ram starts at 0x200M */
0185 dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
0186 dma-coherent;
0187
0188 eth0: ethernet@20000 {
0189 compatible = "marvell,armada-ac5-neta";
0190 reg = <0x0 0x20000 0x0 0x4000>;
0191 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0192 clocks = <&cnm_clock>;
0193 phy-mode = "sgmii";
0194 status = "disabled";
0195 };
0196
0197 eth1: ethernet@24000 {
0198 compatible = "marvell,armada-ac5-neta";
0199 reg = <0x0 0x24000 0x0 0x4000>;
0200 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0201 clocks = <&cnm_clock>;
0202 phy-mode = "sgmii";
0203 status = "disabled";
0204 };
0205
0206 usb0: usb@80000 {
0207 compatible = "marvell,orion-ehci";
0208 reg = <0x0 0x80000 0x0 0x500>;
0209 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0210 status = "disabled";
0211 };
0212
0213 usb1: usb@a0000 {
0214 compatible = "marvell,orion-ehci";
0215 reg = <0x0 0xa0000 0x0 0x500>;
0216 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0217 status = "disabled";
0218 };
0219 };
0220
0221 pinctrl0: pinctrl@80020100 {
0222 compatible = "marvell,ac5-pinctrl";
0223 reg = <0 0x80020100 0 0x20>;
0224
0225 i2c0_pins: i2c0-pins {
0226 marvell,pins = "mpp26", "mpp27";
0227 marvell,function = "i2c0";
0228 };
0229
0230 i2c0_gpio: i2c0-gpio-pins {
0231 marvell,pins = "mpp26", "mpp27";
0232 marvell,function = "gpio";
0233 };
0234
0235 i2c1_pins: i2c1-pins {
0236 marvell,pins = "mpp20", "mpp21";
0237 marvell,function = "i2c1";
0238 };
0239
0240 i2c1_gpio: i2c1-gpio-pins {
0241 marvell,pins = "mpp20", "mpp21";
0242 marvell,function = "i2c1";
0243 };
0244 };
0245
0246 spi0: spi@805a0000 {
0247 compatible = "marvell,armada-3700-spi";
0248 reg = <0x0 0x805a0000 0x0 0x50>;
0249 #address-cells = <0x1>;
0250 #size-cells = <0x0>;
0251 clocks = <&spi_clock>;
0252 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0253 num-cs = <1>;
0254 status = "disabled";
0255 };
0256
0257 spi1: spi@805a8000 {
0258 compatible = "marvell,armada-3700-spi";
0259 reg = <0x0 0x805a8000 0x0 0x50>;
0260 #address-cells = <0x1>;
0261 #size-cells = <0x0>;
0262 clocks = <&spi_clock>;
0263 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0264 num-cs = <1>;
0265 status = "disabled";
0266 };
0267
0268 gic: interrupt-controller@80600000 {
0269 compatible = "arm,gic-v3";
0270 #interrupt-cells = <3>;
0271 interrupt-controller;
0272 reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
0273 <0x0 0x80660000 0x0 0x40000>; /* GICR */
0274 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
0275 };
0276 };
0277
0278 clocks {
0279 cnm_clock: cnm-clock {
0280 compatible = "fixed-clock";
0281 #clock-cells = <0>;
0282 clock-frequency = <328000000>;
0283 };
0284
0285 spi_clock: spi-clock {
0286 compatible = "fixed-clock";
0287 #clock-cells = <0>;
0288 clock-frequency = <200000000>;
0289 };
0290 };
0291 };
