0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * dts file for lg1313 SoC
0004 *
0005 * Copyright (C) 2016, LG Electronics
0006 */
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010
0011 / {
0012 #address-cells = <2>;
0013 #size-cells = <2>;
0014
0015 compatible = "lge,lg1313";
0016 interrupt-parent = <&gic>;
0017
0018 cpus {
0019 #address-cells = <2>;
0020 #size-cells = <0>;
0021
0022 cpu0: cpu@0 {
0023 device_type = "cpu";
0024 compatible = "arm,cortex-a53";
0025 reg = <0x0 0x0>;
0026 next-level-cache = <&L2_0>;
0027 };
0028 cpu1: cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a53";
0031 reg = <0x0 0x1>;
0032 enable-method = "psci";
0033 next-level-cache = <&L2_0>;
0034 };
0035 cpu2: cpu@2 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a53";
0038 reg = <0x0 0x2>;
0039 enable-method = "psci";
0040 next-level-cache = <&L2_0>;
0041 };
0042 cpu3: cpu@3 {
0043 device_type = "cpu";
0044 compatible = "arm,cortex-a53";
0045 reg = <0x0 0x3>;
0046 enable-method = "psci";
0047 next-level-cache = <&L2_0>;
0048 };
0049 L2_0: l2-cache0 {
0050 compatible = "cache";
0051 };
0052 };
0053
0054 psci {
0055 compatible = "arm,psci-0.2", "arm,psci";
0056 method = "smc";
0057 cpu_suspend = <0x84000001>;
0058 cpu_off = <0x84000002>;
0059 cpu_on = <0x84000003>;
0060 };
0061
0062 gic: interrupt-controller@c0001000 {
0063 #interrupt-cells = <3>;
0064 compatible = "arm,gic-400";
0065 interrupt-controller;
0066 reg = <0x0 0xc0001000 0x1000>,
0067 <0x0 0xc0002000 0x2000>,
0068 <0x0 0xc0004000 0x2000>,
0069 <0x0 0xc0006000 0x2000>;
0070 };
0071
0072 pmu {
0073 compatible = "arm,cortex-a53-pmu";
0074 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0075 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
0076 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
0077 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
0078 interrupt-affinity = <&cpu0>,
0079 <&cpu1>,
0080 <&cpu2>,
0081 <&cpu3>;
0082 };
0083
0084 timer {
0085 compatible = "arm,armv8-timer";
0086 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
0087 IRQ_TYPE_LEVEL_LOW)>,
0088 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
0089 IRQ_TYPE_LEVEL_LOW)>,
0090 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
0091 IRQ_TYPE_LEVEL_LOW)>,
0092 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
0093 IRQ_TYPE_LEVEL_LOW)>;
0094 };
0095
0096 clk_bus: clk_bus {
0097 #clock-cells = <0>;
0098
0099 compatible = "fixed-clock";
0100 clock-frequency = <198000000>;
0101 clock-output-names = "BUSCLK";
0102 };
0103
0104 soc {
0105 #address-cells = <2>;
0106 #size-cells = <1>;
0107
0108 compatible = "simple-bus";
0109 interrupt-parent = <&gic>;
0110 ranges;
0111
0112 eth0: ethernet@c3700000 {
0113 compatible = "cdns,gem";
0114 reg = <0x0 0xc3700000 0x1000>;
0115 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0116 clocks = <&clk_bus>, <&clk_bus>;
0117 clock-names = "hclk", "pclk";
0118 phy-mode = "rmii";
0119 /* Filled in by boot */
0120 mac-address = [ 00 00 00 00 00 00 ];
0121 };
0122 };
0123
0124 amba {
0125 #address-cells = <2>;
0126 #size-cells = <1>;
0127 #interrupt-cells = <3>;
0128
0129 compatible = "simple-bus";
0130 interrupt-parent = <&gic>;
0131 ranges;
0132
0133 timers: timer@fd100000 {
0134 compatible = "arm,sp804", "arm,primecell";
0135 reg = <0x0 0xfd100000 0x1000>;
0136 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0137 clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
0138 clock-names = "timer0clk", "timer1clk", "apb_pclk";
0139 };
0140 wdog: watchdog@fd200000 {
0141 compatible = "arm,sp805", "arm,primecell";
0142 reg = <0x0 0xfd200000 0x1000>;
0143 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0144 clocks = <&clk_bus>, <&clk_bus>;
0145 clock-names = "wdog_clk", "apb_pclk";
0146 };
0147 uart0: serial@fe000000 {
0148 compatible = "arm,pl011", "arm,primecell";
0149 reg = <0x0 0xfe000000 0x1000>;
0150 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0151 clocks = <&clk_bus>;
0152 clock-names = "apb_pclk";
0153 status = "disabled";
0154 };
0155 uart1: serial@fe100000 {
0156 compatible = "arm,pl011", "arm,primecell";
0157 reg = <0x0 0xfe100000 0x1000>;
0158 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0159 clocks = <&clk_bus>;
0160 clock-names = "apb_pclk";
0161 status = "disabled";
0162 };
0163 uart2: serial@fe200000 {
0164 compatible = "arm,pl011", "arm,primecell";
0165 reg = <0x0 0xfe200000 0x1000>;
0166 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0167 clocks = <&clk_bus>;
0168 clock-names = "apb_pclk";
0169 status = "disabled";
0170 };
0171 spi0: spi@fe800000 {
0172 compatible = "arm,pl022", "arm,primecell";
0173 reg = <0x0 0xfe800000 0x1000>;
0174 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0175 clocks = <&clk_bus>;
0176 clock-names = "apb_pclk";
0177 };
0178 spi1: spi@fe900000 {
0179 compatible = "arm,pl022", "arm,primecell";
0180 reg = <0x0 0xfe900000 0x1000>;
0181 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0182 clocks = <&clk_bus>;
0183 clock-names = "apb_pclk";
0184 };
0185 dmac0: dma-controller@c1128000 {
0186 compatible = "arm,pl330", "arm,primecell";
0187 reg = <0x0 0xc1128000 0x1000>;
0188 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0189 clocks = <&clk_bus>;
0190 clock-names = "apb_pclk";
0191 #dma-cells = <1>;
0192 };
0193 gpio0: gpio@fd400000 {
0194 #gpio-cells = <2>;
0195 compatible = "arm,pl061", "arm,primecell";
0196 gpio-controller;
0197 reg = <0x0 0xfd400000 0x1000>;
0198 clocks = <&clk_bus>;
0199 clock-names = "apb_pclk";
0200 status = "disabled";
0201 };
0202 gpio1: gpio@fd410000 {
0203 #gpio-cells = <2>;
0204 compatible = "arm,pl061", "arm,primecell";
0205 gpio-controller;
0206 reg = <0x0 0xfd410000 0x1000>;
0207 clocks = <&clk_bus>;
0208 clock-names = "apb_pclk";
0209 status = "disabled";
0210 };
0211 gpio2: gpio@fd420000 {
0212 #gpio-cells = <2>;
0213 compatible = "arm,pl061", "arm,primecell";
0214 gpio-controller;
0215 reg = <0x0 0xfd420000 0x1000>;
0216 clocks = <&clk_bus>;
0217 clock-names = "apb_pclk";
0218 status = "disabled";
0219 };
0220 gpio3: gpio@fd430000 {
0221 #gpio-cells = <2>;
0222 compatible = "arm,pl061", "arm,primecell";
0223 gpio-controller;
0224 reg = <0x0 0xfd430000 0x1000>;
0225 clocks = <&clk_bus>;
0226 clock-names = "apb_pclk";
0227 };
0228 gpio4: gpio@fd440000 {
0229 #gpio-cells = <2>;
0230 compatible = "arm,pl061", "arm,primecell";
0231 gpio-controller;
0232 reg = <0x0 0xfd440000 0x1000>;
0233 clocks = <&clk_bus>;
0234 clock-names = "apb_pclk";
0235 status = "disabled";
0236 };
0237 gpio5: gpio@fd450000 {
0238 #gpio-cells = <2>;
0239 compatible = "arm,pl061", "arm,primecell";
0240 gpio-controller;
0241 reg = <0x0 0xfd450000 0x1000>;
0242 clocks = <&clk_bus>;
0243 clock-names = "apb_pclk";
0244 status = "disabled";
0245 };
0246 gpio6: gpio@fd460000 {
0247 #gpio-cells = <2>;
0248 compatible = "arm,pl061", "arm,primecell";
0249 gpio-controller;
0250 reg = <0x0 0xfd460000 0x1000>;
0251 clocks = <&clk_bus>;
0252 clock-names = "apb_pclk";
0253 status = "disabled";
0254 };
0255 gpio7: gpio@fd470000 {
0256 #gpio-cells = <2>;
0257 compatible = "arm,pl061", "arm,primecell";
0258 gpio-controller;
0259 reg = <0x0 0xfd470000 0x1000>;
0260 clocks = <&clk_bus>;
0261 clock-names = "apb_pclk";
0262 status = "disabled";
0263 };
0264 gpio8: gpio@fd480000 {
0265 #gpio-cells = <2>;
0266 compatible = "arm,pl061", "arm,primecell";
0267 gpio-controller;
0268 reg = <0x0 0xfd480000 0x1000>;
0269 clocks = <&clk_bus>;
0270 clock-names = "apb_pclk";
0271 status = "disabled";
0272 };
0273 gpio9: gpio@fd490000 {
0274 #gpio-cells = <2>;
0275 compatible = "arm,pl061", "arm,primecell";
0276 gpio-controller;
0277 reg = <0x0 0xfd490000 0x1000>;
0278 clocks = <&clk_bus>;
0279 clock-names = "apb_pclk";
0280 status = "disabled";
0281 };
0282 gpio10: gpio@fd4a0000 {
0283 #gpio-cells = <2>;
0284 compatible = "arm,pl061", "arm,primecell";
0285 gpio-controller;
0286 reg = <0x0 0xfd4a0000 0x1000>;
0287 clocks = <&clk_bus>;
0288 clock-names = "apb_pclk";
0289 status = "disabled";
0290 };
0291 gpio11: gpio@fd4b0000 {
0292 #gpio-cells = <2>;
0293 compatible = "arm,pl061", "arm,primecell";
0294 gpio-controller;
0295 reg = <0x0 0xfd4b0000 0x1000>;
0296 clocks = <&clk_bus>;
0297 clock-names = "apb_pclk";
0298 };
0299 gpio12: gpio@fd4c0000 {
0300 #gpio-cells = <2>;
0301 compatible = "arm,pl061", "arm,primecell";
0302 gpio-controller;
0303 reg = <0x0 0xfd4c0000 0x1000>;
0304 clocks = <&clk_bus>;
0305 clock-names = "apb_pclk";
0306 status = "disabled";
0307 };
0308 gpio13: gpio@fd4d0000 {
0309 #gpio-cells = <2>;
0310 compatible = "arm,pl061", "arm,primecell";
0311 gpio-controller;
0312 reg = <0x0 0xfd4d0000 0x1000>;
0313 clocks = <&clk_bus>;
0314 clock-names = "apb_pclk";
0315 status = "disabled";
0316 };
0317 gpio14: gpio@fd4e0000 {
0318 #gpio-cells = <2>;
0319 compatible = "arm,pl061", "arm,primecell";
0320 gpio-controller;
0321 reg = <0x0 0xfd4e0000 0x1000>;
0322 clocks = <&clk_bus>;
0323 clock-names = "apb_pclk";
0324 status = "disabled";
0325 };
0326 gpio15: gpio@fd4f0000 {
0327 #gpio-cells = <2>;
0328 compatible = "arm,pl061", "arm,primecell";
0329 gpio-controller;
0330 reg = <0x0 0xfd4f0000 0x1000>;
0331 clocks = <&clk_bus>;
0332 clock-names = "apb_pclk";
0333 status = "disabled";
0334 };
0335 gpio16: gpio@fd500000 {
0336 #gpio-cells = <2>;
0337 compatible = "arm,pl061", "arm,primecell";
0338 gpio-controller;
0339 reg = <0x0 0xfd500000 0x1000>;
0340 clocks = <&clk_bus>;
0341 clock-names = "apb_pclk";
0342 status = "disabled";
0343 };
0344 gpio17: gpio@fd510000 {
0345 #gpio-cells = <2>;
0346 compatible = "arm,pl061", "arm,primecell";
0347 gpio-controller;
0348 reg = <0x0 0xfd510000 0x1000>;
0349 clocks = <&clk_bus>;
0350 clock-names = "apb_pclk";
0351 };
0352 };
0353 };
