0001 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
0002 /*
0003 * Copyright (C) 2020, Intel Corporation.
0004 *
0005 * Device tree describing Keem Bay SoC.
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009
0010 / {
0011 interrupt-parent = <&gic>;
0012 #address-cells = <2>;
0013 #size-cells = <2>;
0014
0015 cpus {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 cpu@0 {
0020 compatible = "arm,cortex-a53";
0021 device_type = "cpu";
0022 reg = <0x0>;
0023 enable-method = "psci";
0024 };
0025
0026 cpu@1 {
0027 compatible = "arm,cortex-a53";
0028 device_type = "cpu";
0029 reg = <0x1>;
0030 enable-method = "psci";
0031 };
0032
0033 cpu@2 {
0034 compatible = "arm,cortex-a53";
0035 device_type = "cpu";
0036 reg = <0x2>;
0037 enable-method = "psci";
0038 };
0039
0040 cpu@3 {
0041 compatible = "arm,cortex-a53";
0042 device_type = "cpu";
0043 reg = <0x3>;
0044 enable-method = "psci";
0045 };
0046 };
0047
0048 psci {
0049 compatible = "arm,psci-0.2";
0050 method = "smc";
0051 };
0052
0053 gic: interrupt-controller@20500000 {
0054 compatible = "arm,gic-v3";
0055 interrupt-controller;
0056 #interrupt-cells = <3>;
0057 reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */
0058 <0x0 0x20580000 0x0 0x80000>; /* GICR */
0059 /* VGIC maintenance interrupt */
0060 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0061 };
0062
0063 timer {
0064 compatible = "arm,armv8-timer";
0065 /* Secure, non-secure, virtual, and hypervisor */
0066 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
0067 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
0068 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
0069 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
0070 };
0071
0072 pmu {
0073 compatible = "arm,armv8-pmuv3";
0074 interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
0075 };
0076
0077 soc {
0078 compatible = "simple-bus";
0079 #address-cells = <2>;
0080 #size-cells = <2>;
0081 ranges;
0082
0083 uart0: serial@20150000 {
0084 compatible = "snps,dw-apb-uart";
0085 reg = <0x0 0x20150000 0x0 0x100>;
0086 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0087 clock-frequency = <24000000>;
0088 reg-shift = <2>;
0089 reg-io-width = <4>;
0090 status = "disabled";
0091 };
0092
0093 uart1: serial@20160000 {
0094 compatible = "snps,dw-apb-uart";
0095 reg = <0x0 0x20160000 0x0 0x100>;
0096 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0097 clock-frequency = <24000000>;
0098 reg-shift = <2>;
0099 reg-io-width = <4>;
0100 status = "disabled";
0101 };
0102
0103 uart2: serial@20170000 {
0104 compatible = "snps,dw-apb-uart";
0105 reg = <0x0 0x20170000 0x0 0x100>;
0106 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0107 clock-frequency = <24000000>;
0108 reg-shift = <2>;
0109 reg-io-width = <4>;
0110 status = "disabled";
0111 };
0112
0113 uart3: serial@20180000 {
0114 compatible = "snps,dw-apb-uart";
0115 reg = <0x0 0x20180000 0x0 0x100>;
0116 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0117 clock-frequency = <24000000>;
0118 reg-shift = <2>;
0119 reg-io-width = <4>;
0120 status = "disabled";
0121 };
0122 };
0123 };
