0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright 2015-2016 Freescale Semiconductor, Inc.
0004 * Copyright 2016-2018 NXP
0005 */
0006
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008
0009 /memreserve/ 0x80000000 0x00010000;
0010
0011 / {
0012 compatible = "fsl,s32v234";
0013 interrupt-parent = <&gic>;
0014 #address-cells = <2>;
0015 #size-cells = <2>;
0016
0017 aliases {
0018 serial0 = &uart0;
0019 serial1 = &uart1;
0020 };
0021
0022 cpus {
0023 #address-cells = <2>;
0024 #size-cells = <0>;
0025
0026 cpu0: cpu@0 {
0027 device_type = "cpu";
0028 compatible = "arm,cortex-a53";
0029 reg = <0x0 0x0>;
0030 enable-method = "spin-table";
0031 cpu-release-addr = <0x0 0x80000000>;
0032 next-level-cache = <&cluster0_l2_cache>;
0033 };
0034
0035 cpu1: cpu@1 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a53";
0038 reg = <0x0 0x1>;
0039 enable-method = "spin-table";
0040 cpu-release-addr = <0x0 0x80000000>;
0041 next-level-cache = <&cluster0_l2_cache>;
0042 };
0043
0044 cpu2: cpu@100 {
0045 device_type = "cpu";
0046 compatible = "arm,cortex-a53";
0047 reg = <0x0 0x100>;
0048 enable-method = "spin-table";
0049 cpu-release-addr = <0x0 0x80000000>;
0050 next-level-cache = <&cluster1_l2_cache>;
0051 };
0052
0053 cpu3: cpu@101 {
0054 device_type = "cpu";
0055 compatible = "arm,cortex-a53";
0056 reg = <0x0 0x101>;
0057 enable-method = "spin-table";
0058 cpu-release-addr = <0x0 0x80000000>;
0059 next-level-cache = <&cluster1_l2_cache>;
0060 };
0061
0062 cluster0_l2_cache: l2-cache0 {
0063 compatible = "cache";
0064 };
0065
0066 cluster1_l2_cache: l2-cache1 {
0067 compatible = "cache";
0068 };
0069 };
0070
0071 timer {
0072 compatible = "arm,armv8-timer";
0073 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
0074 IRQ_TYPE_LEVEL_LOW)>,
0075 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
0076 IRQ_TYPE_LEVEL_LOW)>,
0077 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
0078 IRQ_TYPE_LEVEL_LOW)>,
0079 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
0080 IRQ_TYPE_LEVEL_LOW)>;
0081 /* clock-frequency might be modified by u-boot, depending on the
0082 * chip version.
0083 */
0084 clock-frequency = <10000000>;
0085 };
0086
0087 gic: interrupt-controller@7d001000 {
0088 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
0089 #interrupt-cells = <3>;
0090 #address-cells = <0>;
0091 interrupt-controller;
0092 reg = <0 0x7d001000 0 0x1000>,
0093 <0 0x7d002000 0 0x2000>,
0094 <0 0x7d004000 0 0x2000>,
0095 <0 0x7d006000 0 0x2000>;
0096 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
0097 IRQ_TYPE_LEVEL_HIGH)>;
0098 };
0099
0100 soc {
0101 #address-cells = <2>;
0102 #size-cells = <2>;
0103 compatible = "simple-bus";
0104 interrupt-parent = <&gic>;
0105 ranges;
0106
0107 aips0: bus@40000000 {
0108 compatible = "simple-bus";
0109 #address-cells = <2>;
0110 #size-cells = <2>;
0111 interrupt-parent = <&gic>;
0112 reg = <0x0 0x40000000 0x0 0x7d000>;
0113 ranges;
0114
0115 uart0: serial@40053000 {
0116 compatible = "fsl,s32v234-linflexuart";
0117 reg = <0x0 0x40053000 0x0 0x1000>;
0118 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
0119 status = "disabled";
0120 };
0121 };
0122
0123 aips1: bus@40080000 {
0124 compatible = "simple-bus";
0125 #address-cells = <2>;
0126 #size-cells = <2>;
0127 interrupt-parent = <&gic>;
0128 reg = <0x0 0x40080000 0x0 0x70000>;
0129 ranges;
0130
0131 uart1: serial@400bc000 {
0132 compatible = "fsl,s32v234-linflexuart";
0133 reg = <0x0 0x400bc000 0x0 0x1000>;
0134 interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
0135 status = "disabled";
0136 };
0137 };
0138 };
0139 };
