0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2022 NXP
0004 */
0005
0006 #include <dt-bindings/clock/imx93-clock.h>
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/input/input.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010
0011 #include "imx93-pinfunc.h"
0012
0013 / {
0014 interrupt-parent = <&gic>;
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 aliases {
0019 mmc0 = &usdhc1;
0020 mmc1 = &usdhc2;
0021 mmc2 = &usdhc3;
0022 serial0 = &lpuart1;
0023 serial1 = &lpuart2;
0024 serial2 = &lpuart3;
0025 serial3 = &lpuart4;
0026 serial4 = &lpuart5;
0027 serial5 = &lpuart6;
0028 serial6 = &lpuart7;
0029 serial7 = &lpuart8;
0030 };
0031
0032 cpus {
0033 #address-cells = <1>;
0034 #size-cells = <0>;
0035
0036 A55_0: cpu@0 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a55";
0039 reg = <0x0>;
0040 enable-method = "psci";
0041 #cooling-cells = <2>;
0042 };
0043
0044 A55_1: cpu@100 {
0045 device_type = "cpu";
0046 compatible = "arm,cortex-a55";
0047 reg = <0x100>;
0048 enable-method = "psci";
0049 #cooling-cells = <2>;
0050 };
0051
0052 };
0053
0054 osc_32k: clock-osc-32k {
0055 compatible = "fixed-clock";
0056 #clock-cells = <0>;
0057 clock-frequency = <32768>;
0058 clock-output-names = "osc_32k";
0059 };
0060
0061 osc_24m: clock-osc-24m {
0062 compatible = "fixed-clock";
0063 #clock-cells = <0>;
0064 clock-frequency = <24000000>;
0065 clock-output-names = "osc_24m";
0066 };
0067
0068 clk_ext1: clock-ext1 {
0069 compatible = "fixed-clock";
0070 #clock-cells = <0>;
0071 clock-frequency = <133000000>;
0072 clock-output-names = "clk_ext1";
0073 };
0074
0075 psci {
0076 compatible = "arm,psci-1.0";
0077 method = "smc";
0078 };
0079
0080 timer {
0081 compatible = "arm,armv8-timer";
0082 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
0083 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
0084 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
0085 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
0086 clock-frequency = <24000000>;
0087 arm,no-tick-in-suspend;
0088 interrupt-parent = <&gic>;
0089 };
0090
0091 gic: interrupt-controller@48000000 {
0092 compatible = "arm,gic-v3";
0093 reg = <0 0x48000000 0 0x10000>,
0094 <0 0x48040000 0 0xc0000>;
0095 #interrupt-cells = <3>;
0096 interrupt-controller;
0097 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0098 interrupt-parent = <&gic>;
0099 };
0100
0101 soc@0 {
0102 compatible = "simple-bus";
0103 #address-cells = <1>;
0104 #size-cells = <1>;
0105 ranges = <0x0 0x0 0x0 0x80000000>,
0106 <0x28000000 0x0 0x28000000 0x10000000>;
0107
0108 aips1: bus@44000000 {
0109 compatible = "fsl,aips-bus", "simple-bus";
0110 reg = <0x44000000 0x800000>;
0111 #address-cells = <1>;
0112 #size-cells = <1>;
0113 ranges;
0114
0115 mu1: mailbox@44230000 {
0116 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
0117 reg = <0x44230000 0x10000>;
0118 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0119 #mbox-cells = <2>;
0120 status = "disabled";
0121 };
0122
0123 system_counter: timer@44290000 {
0124 compatible = "nxp,sysctr-timer";
0125 reg = <0x44290000 0x30000>;
0126 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0127 clocks = <&osc_24m>;
0128 clock-names = "per";
0129 };
0130
0131 lpuart1: serial@44380000 {
0132 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
0133 reg = <0x44380000 0x1000>;
0134 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0135 clocks = <&clk IMX93_CLK_LPUART1_GATE>;
0136 clock-names = "ipg";
0137 status = "disabled";
0138 };
0139
0140 lpuart2: serial@44390000 {
0141 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
0142 reg = <0x44390000 0x1000>;
0143 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0144 clocks = <&clk IMX93_CLK_LPUART2_GATE>;
0145 clock-names = "ipg";
0146 status = "disabled";
0147 };
0148
0149 iomuxc: pinctrl@443c0000 {
0150 compatible = "fsl,imx93-iomuxc";
0151 reg = <0x443c0000 0x10000>;
0152 status = "okay";
0153 };
0154
0155 clk: clock-controller@44450000 {
0156 compatible = "fsl,imx93-ccm";
0157 reg = <0x44450000 0x10000>;
0158 #clock-cells = <1>;
0159 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
0160 clock-names = "osc_32k", "osc_24m", "clk_ext1";
0161 status = "okay";
0162 };
0163
0164 anatop: anatop@44480000 {
0165 compatible = "fsl,imx93-anatop", "syscon";
0166 reg = <0x44480000 0x10000>;
0167 };
0168 };
0169
0170 aips2: bus@42000000 {
0171 compatible = "fsl,aips-bus", "simple-bus";
0172 reg = <0x42000000 0x800000>;
0173 #address-cells = <1>;
0174 #size-cells = <1>;
0175 ranges;
0176
0177 mu2: mailbox@42440000 {
0178 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
0179 reg = <0x42440000 0x10000>;
0180 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0181 #mbox-cells = <2>;
0182 status = "disabled";
0183 };
0184
0185 lpuart3: serial@42570000 {
0186 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
0187 reg = <0x42570000 0x1000>;
0188 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0189 clocks = <&clk IMX93_CLK_LPUART3_GATE>;
0190 clock-names = "ipg";
0191 status = "disabled";
0192 };
0193
0194 lpuart4: serial@42580000 {
0195 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
0196 reg = <0x42580000 0x1000>;
0197 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0198 clocks = <&clk IMX93_CLK_LPUART4_GATE>;
0199 clock-names = "ipg";
0200 status = "disabled";
0201 };
0202
0203 lpuart5: serial@42590000 {
0204 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
0205 reg = <0x42590000 0x1000>;
0206 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0207 clocks = <&clk IMX93_CLK_LPUART5_GATE>;
0208 clock-names = "ipg";
0209 status = "disabled";
0210 };
0211
0212 lpuart6: serial@425a0000 {
0213 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
0214 reg = <0x425a0000 0x1000>;
0215 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0216 clocks = <&clk IMX93_CLK_LPUART6_GATE>;
0217 clock-names = "ipg";
0218 status = "disabled";
0219 };
0220
0221 lpuart7: serial@42690000 {
0222 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
0223 reg = <0x42690000 0x1000>;
0224 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
0225 clocks = <&clk IMX93_CLK_LPUART7_GATE>;
0226 clock-names = "ipg";
0227 status = "disabled";
0228 };
0229
0230 lpuart8: serial@426a0000 {
0231 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
0232 reg = <0x426a0000 0x1000>;
0233 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
0234 clocks = <&clk IMX93_CLK_LPUART8_GATE>;
0235 clock-names = "ipg";
0236 status = "disabled";
0237 };
0238 };
0239
0240 aips3: bus@42800000 {
0241 compatible = "fsl,aips-bus", "simple-bus";
0242 reg = <0x42800000 0x800000>;
0243 #address-cells = <1>;
0244 #size-cells = <1>;
0245 ranges;
0246
0247 usdhc1: mmc@42850000 {
0248 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
0249 reg = <0x42850000 0x10000>;
0250 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0251 clocks = <&clk IMX93_CLK_DUMMY>,
0252 <&clk IMX93_CLK_DUMMY>,
0253 <&clk IMX93_CLK_USDHC1_GATE>;
0254 clock-names = "ipg", "ahb", "per";
0255 bus-width = <8>;
0256 fsl,tuning-start-tap = <20>;
0257 fsl,tuning-step= <2>;
0258 status = "disabled";
0259 };
0260
0261 usdhc2: mmc@42860000 {
0262 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
0263 reg = <0x42860000 0x10000>;
0264 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0265 clocks = <&clk IMX93_CLK_DUMMY>,
0266 <&clk IMX93_CLK_DUMMY>,
0267 <&clk IMX93_CLK_USDHC2_GATE>;
0268 clock-names = "ipg", "ahb", "per";
0269 bus-width = <4>;
0270 fsl,tuning-start-tap = <20>;
0271 fsl,tuning-step= <2>;
0272 status = "disabled";
0273 };
0274
0275 usdhc3: mmc@428b0000 {
0276 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
0277 reg = <0x428b0000 0x10000>;
0278 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
0279 clocks = <&clk IMX93_CLK_DUMMY>,
0280 <&clk IMX93_CLK_DUMMY>,
0281 <&clk IMX93_CLK_USDHC3_GATE>;
0282 clock-names = "ipg", "ahb", "per";
0283 bus-width = <4>;
0284 fsl,tuning-start-tap = <20>;
0285 fsl,tuning-step= <2>;
0286 status = "disabled";
0287 };
0288 };
0289
0290 gpio2: gpio@43810080 {
0291 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
0292 reg = <0x43810080 0x1000>, <0x43810040 0x40>;
0293 gpio-controller;
0294 #gpio-cells = <2>;
0295 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0296 interrupt-controller;
0297 #interrupt-cells = <2>;
0298 gpio-ranges = <&iomuxc 0 32 32>;
0299 };
0300
0301 gpio3: gpio@43820080 {
0302 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
0303 reg = <0x43820080 0x1000>, <0x43820040 0x40>;
0304 gpio-controller;
0305 #gpio-cells = <2>;
0306 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0307 interrupt-controller;
0308 #interrupt-cells = <2>;
0309 gpio-ranges = <&iomuxc 0 64 32>;
0310 };
0311
0312 gpio4: gpio@43830080 {
0313 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
0314 reg = <0x43830080 0x1000>, <0x43830040 0x40>;
0315 gpio-controller;
0316 #gpio-cells = <2>;
0317 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
0318 interrupt-controller;
0319 #interrupt-cells = <2>;
0320 gpio-ranges = <&iomuxc 0 96 32>;
0321 };
0322
0323 gpio1: gpio@47400080 {
0324 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
0325 reg = <0x47400080 0x1000>, <0x47400040 0x40>;
0326 gpio-controller;
0327 #gpio-cells = <2>;
0328 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0329 interrupt-controller;
0330 #interrupt-cells = <2>;
0331 gpio-ranges = <&iomuxc 0 0 32>;
0332 };
0333 };
0334 };
