0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2021 NXP
0004 */
0005
0006 #include <dt-bindings/clock/imx8ulp-clock.h>
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/power/imx8ulp-power.h>
0010
0011 #include "imx8ulp-pinfunc.h"
0012
0013 / {
0014 interrupt-parent = <&gic>;
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 aliases {
0019 gpio0 = &gpiod;
0020 gpio1 = &gpioe;
0021 gpio2 = &gpiof;
0022 mmc0 = &usdhc0;
0023 mmc1 = &usdhc1;
0024 mmc2 = &usdhc2;
0025 serial0 = &lpuart4;
0026 serial1 = &lpuart5;
0027 serial2 = &lpuart6;
0028 serial3 = &lpuart7;
0029 };
0030
0031 cpus {
0032 #address-cells = <2>;
0033 #size-cells = <0>;
0034
0035 A35_0: cpu@0 {
0036 device_type = "cpu";
0037 compatible = "arm,cortex-a35";
0038 reg = <0x0 0x0>;
0039 enable-method = "psci";
0040 next-level-cache = <&A35_L2>;
0041 };
0042
0043 A35_1: cpu@1 {
0044 device_type = "cpu";
0045 compatible = "arm,cortex-a35";
0046 reg = <0x0 0x1>;
0047 enable-method = "psci";
0048 next-level-cache = <&A35_L2>;
0049 };
0050
0051 A35_L2: l2-cache0 {
0052 compatible = "cache";
0053 };
0054 };
0055
0056 gic: interrupt-controller@2d400000 {
0057 compatible = "arm,gic-v3";
0058 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
0059 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
0060 #interrupt-cells = <3>;
0061 interrupt-controller;
0062 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0063 };
0064
0065 psci {
0066 compatible = "arm,psci-1.0";
0067 method = "smc";
0068 };
0069
0070 timer {
0071 compatible = "arm,armv8-timer";
0072 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
0073 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
0074 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
0075 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
0076 };
0077
0078 frosc: clock-frosc {
0079 compatible = "fixed-clock";
0080 clock-frequency = <192000000>;
0081 clock-output-names = "frosc";
0082 #clock-cells = <0>;
0083 };
0084
0085 lposc: clock-lposc {
0086 compatible = "fixed-clock";
0087 clock-frequency = <1000000>;
0088 clock-output-names = "lposc";
0089 #clock-cells = <0>;
0090 };
0091
0092 rosc: clock-rosc {
0093 compatible = "fixed-clock";
0094 clock-frequency = <32768>;
0095 clock-output-names = "rosc";
0096 #clock-cells = <0>;
0097 };
0098
0099 sosc: clock-sosc {
0100 compatible = "fixed-clock";
0101 clock-frequency = <24000000>;
0102 clock-output-names = "sosc";
0103 #clock-cells = <0>;
0104 };
0105
0106 sram@2201f000 {
0107 compatible = "mmio-sram";
0108 reg = <0x0 0x2201f000 0x0 0x1000>;
0109
0110 #address-cells = <1>;
0111 #size-cells = <1>;
0112 ranges = <0 0x0 0x2201f000 0x1000>;
0113
0114 scmi_buf: scmi-buf@0 {
0115 compatible = "arm,scmi-shmem";
0116 reg = <0x0 0x400>;
0117 };
0118 };
0119
0120 firmware {
0121 scmi {
0122 compatible = "arm,scmi-smc";
0123 arm,smc-id = <0xc20000fe>;
0124 #address-cells = <1>;
0125 #size-cells = <0>;
0126 shmem = <&scmi_buf>;
0127
0128 scmi_devpd: protocol@11 {
0129 reg = <0x11>;
0130 #power-domain-cells = <1>;
0131 };
0132
0133 scmi_sensor: protocol@15 {
0134 reg = <0x15>;
0135 #thermal-sensor-cells = <1>;
0136 };
0137 };
0138 };
0139
0140 soc: soc@0 {
0141 compatible = "simple-bus";
0142 #address-cells = <1>;
0143 #size-cells = <1>;
0144 ranges = <0x0 0x0 0x0 0x40000000>;
0145
0146 per_bridge3: bus@29000000 {
0147 compatible = "simple-bus";
0148 reg = <0x29000000 0x800000>;
0149 #address-cells = <1>;
0150 #size-cells = <1>;
0151 ranges;
0152
0153 wdog3: watchdog@292a0000 {
0154 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
0155 reg = <0x292a0000 0x10000>;
0156 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0157 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
0158 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
0159 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
0160 timeout-sec = <40>;
0161 };
0162
0163 cgc1: clock-controller@292c0000 {
0164 compatible = "fsl,imx8ulp-cgc1";
0165 reg = <0x292c0000 0x10000>;
0166 clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
0167 clock-names = "rosc", "sosc", "frosc", "lposc";
0168 #clock-cells = <1>;
0169 };
0170
0171 pcc3: clock-controller@292d0000 {
0172 compatible = "fsl,imx8ulp-pcc3";
0173 reg = <0x292d0000 0x10000>;
0174 #clock-cells = <1>;
0175 #reset-cells = <1>;
0176 };
0177
0178 tpm5: tpm@29340000 {
0179 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
0180 reg = <0x29340000 0x1000>;
0181 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0182 clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
0183 <&pcc3 IMX8ULP_CLK_TPM5>;
0184 clock-names = "ipg", "per";
0185 status = "disabled";
0186 };
0187
0188 lpi2c4: i2c@29370000 {
0189 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
0190 reg = <0x29370000 0x10000>;
0191 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0192 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
0193 <&pcc3 IMX8ULP_CLK_LPI2C4>;
0194 clock-names = "per", "ipg";
0195 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
0196 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
0197 assigned-clock-rates = <48000000>;
0198 status = "disabled";
0199 };
0200
0201 lpi2c5: i2c@29380000 {
0202 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
0203 reg = <0x29380000 0x10000>;
0204 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0205 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
0206 <&pcc3 IMX8ULP_CLK_LPI2C5>;
0207 clock-names = "per", "ipg";
0208 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
0209 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
0210 assigned-clock-rates = <48000000>;
0211 status = "disabled";
0212 };
0213
0214 lpuart4: serial@29390000 {
0215 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
0216 reg = <0x29390000 0x1000>;
0217 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0218 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
0219 clock-names = "ipg";
0220 status = "disabled";
0221 };
0222
0223 lpuart5: serial@293a0000 {
0224 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
0225 reg = <0x293a0000 0x1000>;
0226 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0227 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
0228 clock-names = "ipg";
0229 status = "disabled";
0230 };
0231
0232 lpspi4: spi@293b0000 {
0233 #address-cells = <1>;
0234 #size-cells = <0>;
0235 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
0236 reg = <0x293b0000 0x10000>;
0237 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0238 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
0239 <&pcc3 IMX8ULP_CLK_LPSPI4>;
0240 clock-names = "per", "ipg";
0241 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
0242 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
0243 assigned-clock-rates = <16000000>;
0244 status = "disabled";
0245 };
0246
0247 lpspi5: spi@293c0000 {
0248 #address-cells = <1>;
0249 #size-cells = <0>;
0250 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
0251 reg = <0x293c0000 0x10000>;
0252 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0253 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
0254 <&pcc3 IMX8ULP_CLK_LPSPI5>;
0255 clock-names = "per", "ipg";
0256 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
0257 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
0258 assigned-clock-rates = <16000000>;
0259 status = "disabled";
0260 };
0261 };
0262
0263 per_bridge4: bus@29800000 {
0264 compatible = "simple-bus";
0265 reg = <0x29800000 0x800000>;
0266 #address-cells = <1>;
0267 #size-cells = <1>;
0268 ranges;
0269
0270 pcc4: clock-controller@29800000 {
0271 compatible = "fsl,imx8ulp-pcc4";
0272 reg = <0x29800000 0x10000>;
0273 #clock-cells = <1>;
0274 #reset-cells = <1>;
0275 };
0276
0277 lpi2c6: i2c@29840000 {
0278 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
0279 reg = <0x29840000 0x10000>;
0280 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0281 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
0282 <&pcc4 IMX8ULP_CLK_LPI2C6>;
0283 clock-names = "per", "ipg";
0284 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
0285 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
0286 assigned-clock-rates = <48000000>;
0287 status = "disabled";
0288 };
0289
0290 lpi2c7: i2c@29850000 {
0291 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
0292 reg = <0x29850000 0x10000>;
0293 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0294 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
0295 <&pcc4 IMX8ULP_CLK_LPI2C7>;
0296 clock-names = "per", "ipg";
0297 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
0298 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
0299 assigned-clock-rates = <48000000>;
0300 status = "disabled";
0301 };
0302
0303 lpuart6: serial@29860000 {
0304 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
0305 reg = <0x29860000 0x1000>;
0306 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0307 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
0308 clock-names = "ipg";
0309 status = "disabled";
0310 };
0311
0312 lpuart7: serial@29870000 {
0313 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
0314 reg = <0x29870000 0x1000>;
0315 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0316 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
0317 clock-names = "ipg";
0318 status = "disabled";
0319 };
0320
0321 iomuxc1: pinctrl@298c0000 {
0322 compatible = "fsl,imx8ulp-iomuxc1";
0323 reg = <0x298c0000 0x10000>;
0324 };
0325
0326 usdhc0: mmc@298d0000 {
0327 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
0328 reg = <0x298d0000 0x10000>;
0329 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0330 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
0331 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
0332 <&pcc4 IMX8ULP_CLK_USDHC0>;
0333 clock-names = "ipg", "ahb", "per";
0334 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
0335 fsl,tuning-start-tap = <20>;
0336 fsl,tuning-step = <2>;
0337 bus-width = <4>;
0338 status = "disabled";
0339 };
0340
0341 usdhc1: mmc@298e0000 {
0342 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
0343 reg = <0x298e0000 0x10000>;
0344 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0345 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
0346 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
0347 <&pcc4 IMX8ULP_CLK_USDHC1>;
0348 clock-names = "ipg", "ahb", "per";
0349 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
0350 fsl,tuning-start-tap = <20>;
0351 fsl,tuning-step = <2>;
0352 bus-width = <4>;
0353 status = "disabled";
0354 };
0355
0356 usdhc2: mmc@298f0000 {
0357 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
0358 reg = <0x298f0000 0x10000>;
0359 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0360 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
0361 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
0362 <&pcc4 IMX8ULP_CLK_USDHC2>;
0363 clock-names = "ipg", "ahb", "per";
0364 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
0365 fsl,tuning-start-tap = <20>;
0366 fsl,tuning-step = <2>;
0367 bus-width = <4>;
0368 status = "disabled";
0369 };
0370 };
0371
0372 gpioe: gpio@2d000080 {
0373 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
0374 reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
0375 gpio-controller;
0376 #gpio-cells = <2>;
0377 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
0378 interrupt-controller;
0379 #interrupt-cells = <2>;
0380 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
0381 <&pcc4 IMX8ULP_CLK_PCTLE>;
0382 clock-names = "gpio", "port";
0383 gpio-ranges = <&iomuxc1 0 32 24>;
0384 };
0385
0386 gpiof: gpio@2d010080 {
0387 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
0388 reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
0389 gpio-controller;
0390 #gpio-cells = <2>;
0391 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
0392 interrupt-controller;
0393 #interrupt-cells = <2>;
0394 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
0395 <&pcc4 IMX8ULP_CLK_PCTLF>;
0396 clock-names = "gpio", "port";
0397 gpio-ranges = <&iomuxc1 0 64 32>;
0398 };
0399
0400 per_bridge5: bus@2d800000 {
0401 compatible = "simple-bus";
0402 reg = <0x2d800000 0x800000>;
0403 #address-cells = <1>;
0404 #size-cells = <1>;
0405 ranges;
0406
0407 cgc2: clock-controller@2da60000 {
0408 compatible = "fsl,imx8ulp-cgc2";
0409 reg = <0x2da60000 0x10000>;
0410 clocks = <&sosc>, <&frosc>;
0411 clock-names = "sosc", "frosc";
0412 #clock-cells = <1>;
0413 };
0414
0415 pcc5: clock-controller@2da70000 {
0416 compatible = "fsl,imx8ulp-pcc5";
0417 reg = <0x2da70000 0x10000>;
0418 #clock-cells = <1>;
0419 #reset-cells = <1>;
0420 };
0421 };
0422
0423 gpiod: gpio@2e200080 {
0424 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
0425 reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
0426 gpio-controller;
0427 #gpio-cells = <2>;
0428 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0429 interrupt-controller;
0430 #interrupt-cells = <2>;
0431 clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
0432 <&pcc5 IMX8ULP_CLK_RGPIOD>;
0433 clock-names = "gpio", "port";
0434 gpio-ranges = <&iomuxc1 0 0 24>;
0435 };
0436 };
0437 };
