0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2021 NXP
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx8ulp.dtsi"
0009
0010 / {
0011 model = "NXP i.MX8ULP EVK";
0012 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
0013
0014 chosen {
0015 stdout-path = &lpuart5;
0016 };
0017
0018 memory@80000000 {
0019 device_type = "memory";
0020 reg = <0x0 0x80000000 0 0x80000000>;
0021 };
0022 };
0023
0024 &lpuart5 {
0025 /* console */
0026 pinctrl-names = "default", "sleep";
0027 pinctrl-0 = <&pinctrl_lpuart5>;
0028 pinctrl-1 = <&pinctrl_lpuart5>;
0029 status = "okay";
0030 };
0031
0032 &usdhc0 {
0033 pinctrl-names = "default", "sleep";
0034 pinctrl-0 = <&pinctrl_usdhc0>;
0035 pinctrl-1 = <&pinctrl_usdhc0>;
0036 non-removable;
0037 bus-width = <8>;
0038 status = "okay";
0039 };
0040
0041 &iomuxc1 {
0042 pinctrl_lpuart5: lpuart5grp {
0043 fsl,pins = <
0044 MX8ULP_PAD_PTF14__LPUART5_TX 0x3
0045 MX8ULP_PAD_PTF15__LPUART5_RX 0x3
0046 >;
0047 };
0048
0049 pinctrl_usdhc0: usdhc0grp {
0050 fsl,pins = <
0051 MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
0052 MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
0053 MX8ULP_PAD_PTD10__SDHC0_D0 0x43
0054 MX8ULP_PAD_PTD9__SDHC0_D1 0x43
0055 MX8ULP_PAD_PTD8__SDHC0_D2 0x43
0056 MX8ULP_PAD_PTD7__SDHC0_D3 0x43
0057 MX8ULP_PAD_PTD6__SDHC0_D4 0x43
0058 MX8ULP_PAD_PTD5__SDHC0_D5 0x43
0059 MX8ULP_PAD_PTD4__SDHC0_D6 0x43
0060 MX8ULP_PAD_PTD3__SDHC0_D7 0x43
0061 MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
0062 >;
0063 };
0064 };
