0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright (C) 2016 Freescale Semiconductor, Inc.
0004 * Copyright 2017-2020 NXP
0005 * Dong Aisheng <aisheng.dong@nxp.com>
0006 */
0007
0008 #include <dt-bindings/clock/imx8-clock.h>
0009 #include <dt-bindings/clock/imx8-lpcg.h>
0010 #include <dt-bindings/firmware/imx/rsrc.h>
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/input/input.h>
0013 #include <dt-bindings/interrupt-controller/arm-gic.h>
0014 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
0015 #include <dt-bindings/thermal/thermal.h>
0016
0017 / {
0018 interrupt-parent = <&gic>;
0019 #address-cells = <2>;
0020 #size-cells = <2>;
0021
0022 aliases {
0023 ethernet0 = &fec1;
0024 ethernet1 = &fec2;
0025 gpio0 = &lsio_gpio0;
0026 gpio1 = &lsio_gpio1;
0027 gpio2 = &lsio_gpio2;
0028 gpio3 = &lsio_gpio3;
0029 gpio4 = &lsio_gpio4;
0030 gpio5 = &lsio_gpio5;
0031 gpio6 = &lsio_gpio6;
0032 gpio7 = &lsio_gpio7;
0033 i2c0 = &i2c0;
0034 i2c1 = &i2c1;
0035 i2c2 = &i2c2;
0036 i2c3 = &i2c3;
0037 mmc0 = &usdhc1;
0038 mmc1 = &usdhc2;
0039 mmc2 = &usdhc3;
0040 mu0 = &lsio_mu0;
0041 mu1 = &lsio_mu1;
0042 mu2 = &lsio_mu2;
0043 mu3 = &lsio_mu3;
0044 mu4 = &lsio_mu4;
0045 serial0 = &lpuart0;
0046 serial1 = &lpuart1;
0047 serial2 = &lpuart2;
0048 serial3 = &lpuart3;
0049 vpu_core0 = &vpu_core0;
0050 vpu_core1 = &vpu_core1;
0051 vpu_core2 = &vpu_core2;
0052 };
0053
0054 cpus {
0055 #address-cells = <2>;
0056 #size-cells = <0>;
0057
0058 /* We have 1 clusters with 4 Cortex-A35 cores */
0059 A35_0: cpu@0 {
0060 device_type = "cpu";
0061 compatible = "arm,cortex-a35";
0062 reg = <0x0 0x0>;
0063 enable-method = "psci";
0064 i-cache-size = <0x8000>;
0065 i-cache-line-size = <64>;
0066 i-cache-sets = <256>;
0067 d-cache-size = <0x8000>;
0068 d-cache-line-size = <64>;
0069 d-cache-sets = <128>;
0070 next-level-cache = <&A35_L2>;
0071 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
0072 operating-points-v2 = <&a35_opp_table>;
0073 #cooling-cells = <2>;
0074 };
0075
0076 A35_1: cpu@1 {
0077 device_type = "cpu";
0078 compatible = "arm,cortex-a35";
0079 reg = <0x0 0x1>;
0080 enable-method = "psci";
0081 i-cache-size = <0x8000>;
0082 i-cache-line-size = <64>;
0083 i-cache-sets = <256>;
0084 d-cache-size = <0x8000>;
0085 d-cache-line-size = <64>;
0086 d-cache-sets = <128>;
0087 next-level-cache = <&A35_L2>;
0088 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
0089 operating-points-v2 = <&a35_opp_table>;
0090 #cooling-cells = <2>;
0091 };
0092
0093 A35_2: cpu@2 {
0094 device_type = "cpu";
0095 compatible = "arm,cortex-a35";
0096 reg = <0x0 0x2>;
0097 enable-method = "psci";
0098 i-cache-size = <0x8000>;
0099 i-cache-line-size = <64>;
0100 i-cache-sets = <256>;
0101 d-cache-size = <0x8000>;
0102 d-cache-line-size = <64>;
0103 d-cache-sets = <128>;
0104 next-level-cache = <&A35_L2>;
0105 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
0106 operating-points-v2 = <&a35_opp_table>;
0107 #cooling-cells = <2>;
0108 };
0109
0110 A35_3: cpu@3 {
0111 device_type = "cpu";
0112 compatible = "arm,cortex-a35";
0113 reg = <0x0 0x3>;
0114 enable-method = "psci";
0115 i-cache-size = <0x8000>;
0116 i-cache-line-size = <64>;
0117 i-cache-sets = <256>;
0118 d-cache-size = <0x8000>;
0119 d-cache-line-size = <64>;
0120 d-cache-sets = <128>;
0121 next-level-cache = <&A35_L2>;
0122 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
0123 operating-points-v2 = <&a35_opp_table>;
0124 #cooling-cells = <2>;
0125 };
0126
0127 A35_L2: l2-cache0 {
0128 compatible = "cache";
0129 cache-level = <2>;
0130 cache-size = <0x80000>;
0131 cache-line-size = <64>;
0132 cache-sets = <1024>;
0133 };
0134 };
0135
0136 a35_opp_table: opp-table {
0137 compatible = "operating-points-v2";
0138 opp-shared;
0139
0140 opp-900000000 {
0141 opp-hz = /bits/ 64 <900000000>;
0142 opp-microvolt = <1000000>;
0143 clock-latency-ns = <150000>;
0144 };
0145
0146 opp-1200000000 {
0147 opp-hz = /bits/ 64 <1200000000>;
0148 opp-microvolt = <1100000>;
0149 clock-latency-ns = <150000>;
0150 opp-suspend;
0151 };
0152 };
0153
0154 gic: interrupt-controller@51a00000 {
0155 compatible = "arm,gic-v3";
0156 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
0157 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
0158 #interrupt-cells = <3>;
0159 interrupt-controller;
0160 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0161 };
0162
0163 reserved-memory {
0164 #address-cells = <2>;
0165 #size-cells = <2>;
0166 ranges;
0167
0168 decoder_boot: decoder-boot@84000000 {
0169 reg = <0 0x84000000 0 0x2000000>;
0170 no-map;
0171 };
0172
0173 encoder_boot: encoder-boot@86000000 {
0174 reg = <0 0x86000000 0 0x200000>;
0175 no-map;
0176 };
0177
0178 decoder_rpc: decoder-rpc@92000000 {
0179 reg = <0 0x92000000 0 0x100000>;
0180 no-map;
0181 };
0182
0183 dsp_reserved: dsp@92400000 {
0184 reg = <0 0x92400000 0 0x2000000>;
0185 no-map;
0186 };
0187
0188 encoder_rpc: encoder-rpc@94400000 {
0189 reg = <0 0x94400000 0 0x700000>;
0190 no-map;
0191 };
0192 };
0193
0194 pmu {
0195 compatible = "arm,cortex-a35-pmu";
0196 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0197 };
0198
0199 psci {
0200 compatible = "arm,psci-1.0";
0201 method = "smc";
0202 };
0203
0204 system-controller {
0205 compatible = "fsl,imx-scu";
0206 mbox-names = "tx0",
0207 "rx0",
0208 "gip3";
0209 mboxes = <&lsio_mu1 0 0
0210 &lsio_mu1 1 0
0211 &lsio_mu1 3 3>;
0212
0213 pd: power-controller {
0214 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
0215 #power-domain-cells = <1>;
0216 };
0217
0218 clk: clock-controller {
0219 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
0220 #clock-cells = <2>;
0221 };
0222
0223 iomuxc: pinctrl {
0224 compatible = "fsl,imx8qxp-iomuxc";
0225 };
0226
0227 ocotp: ocotp {
0228 compatible = "fsl,imx8qxp-scu-ocotp";
0229 #address-cells = <1>;
0230 #size-cells = <1>;
0231 };
0232
0233 scu_key: keys {
0234 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
0235 linux,keycodes = <KEY_POWER>;
0236 status = "disabled";
0237 };
0238
0239 rtc: rtc {
0240 compatible = "fsl,imx8qxp-sc-rtc";
0241 };
0242
0243 watchdog {
0244 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
0245 timeout-sec = <60>;
0246 };
0247
0248 tsens: thermal-sensor {
0249 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
0250 #thermal-sensor-cells = <1>;
0251 };
0252 };
0253
0254 timer {
0255 compatible = "arm,armv8-timer";
0256 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
0257 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
0258 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
0259 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
0260 };
0261
0262 xtal32k: clock-xtal32k {
0263 compatible = "fixed-clock";
0264 #clock-cells = <0>;
0265 clock-frequency = <32768>;
0266 clock-output-names = "xtal_32KHz";
0267 };
0268
0269 xtal24m: clock-xtal24m {
0270 compatible = "fixed-clock";
0271 #clock-cells = <0>;
0272 clock-frequency = <24000000>;
0273 clock-output-names = "xtal_24MHz";
0274 };
0275
0276 thermal_zones: thermal-zones {
0277 cpu0-thermal {
0278 polling-delay-passive = <250>;
0279 polling-delay = <2000>;
0280 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
0281
0282 trips {
0283 cpu_alert0: trip0 {
0284 temperature = <107000>;
0285 hysteresis = <2000>;
0286 type = "passive";
0287 };
0288
0289 cpu_crit0: trip1 {
0290 temperature = <127000>;
0291 hysteresis = <2000>;
0292 type = "critical";
0293 };
0294 };
0295
0296 cooling-maps {
0297 map0 {
0298 trip = <&cpu_alert0>;
0299 cooling-device =
0300 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0301 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0302 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0303 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0304 };
0305 };
0306 };
0307 };
0308
0309 /* sorted in register address */
0310 #include "imx8-ss-img.dtsi"
0311 #include "imx8-ss-vpu.dtsi"
0312 #include "imx8-ss-adma.dtsi"
0313 #include "imx8-ss-conn.dtsi"
0314 #include "imx8-ss-ddr.dtsi"
0315 #include "imx8-ss-lsio.dtsi"
0316 };
0317
0318 #include "imx8qxp-ss-img.dtsi"
0319 #include "imx8qxp-ss-adma.dtsi"
0320 #include "imx8qxp-ss-conn.dtsi"
0321 #include "imx8qxp-ss-lsio.dtsi"
