0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2017~2018 NXP
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx8qxp.dtsi"
0009
0010 / {
0011 model = "Freescale i.MX8QXP MEK";
0012 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
0013
0014 chosen {
0015 stdout-path = &lpuart0;
0016 };
0017
0018 memory@80000000 {
0019 device_type = "memory";
0020 reg = <0x00000000 0x80000000 0 0x40000000>;
0021 };
0022
0023 reg_usdhc2_vmmc: usdhc2-vmmc {
0024 compatible = "regulator-fixed";
0025 regulator-name = "SD1_SPWR";
0026 regulator-min-microvolt = <3000000>;
0027 regulator-max-microvolt = <3000000>;
0028 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
0029 enable-active-high;
0030 };
0031 };
0032
0033 &dsp {
0034 status = "okay";
0035 };
0036
0037 &fec1 {
0038 pinctrl-names = "default";
0039 pinctrl-0 = <&pinctrl_fec1>;
0040 phy-mode = "rgmii-id";
0041 phy-handle = <ðphy0>;
0042 fsl,magic-packet;
0043 status = "okay";
0044
0045 mdio {
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048
0049 ethphy0: ethernet-phy@0 {
0050 compatible = "ethernet-phy-ieee802.3-c22";
0051 reg = <0>;
0052 };
0053 };
0054 };
0055
0056 &i2c1 {
0057 #address-cells = <1>;
0058 #size-cells = <0>;
0059 clock-frequency = <100000>;
0060 pinctrl-names = "default";
0061 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
0062 status = "okay";
0063
0064 i2c-switch@71 {
0065 compatible = "nxp,pca9646", "nxp,pca9546";
0066 #address-cells = <1>;
0067 #size-cells = <0>;
0068 reg = <0x71>;
0069 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
0070
0071 i2c@0 {
0072 #address-cells = <1>;
0073 #size-cells = <0>;
0074 reg = <0>;
0075
0076 max7322: gpio@68 {
0077 compatible = "maxim,max7322";
0078 reg = <0x68>;
0079 gpio-controller;
0080 #gpio-cells = <2>;
0081 };
0082 };
0083
0084 i2c@1 {
0085 #address-cells = <1>;
0086 #size-cells = <0>;
0087 reg = <1>;
0088 };
0089
0090 i2c@2 {
0091 #address-cells = <1>;
0092 #size-cells = <0>;
0093 reg = <2>;
0094
0095 pressure-sensor@60 {
0096 compatible = "fsl,mpl3115";
0097 reg = <0x60>;
0098 };
0099 };
0100
0101 i2c@3 {
0102 #address-cells = <1>;
0103 #size-cells = <0>;
0104 reg = <3>;
0105
0106 pca9557_a: gpio@1a {
0107 compatible = "nxp,pca9557";
0108 reg = <0x1a>;
0109 gpio-controller;
0110 #gpio-cells = <2>;
0111 };
0112
0113 pca9557_b: gpio@1d {
0114 compatible = "nxp,pca9557";
0115 reg = <0x1d>;
0116 gpio-controller;
0117 #gpio-cells = <2>;
0118 };
0119
0120 light-sensor@44 {
0121 pinctrl-names = "default";
0122 pinctrl-0 = <&pinctrl_isl29023>;
0123 compatible = "isil,isl29023";
0124 reg = <0x44>;
0125 interrupt-parent = <&lsio_gpio1>;
0126 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
0127 };
0128 };
0129 };
0130 };
0131
0132 &lpuart0 {
0133 pinctrl-names = "default";
0134 pinctrl-0 = <&pinctrl_lpuart0>;
0135 status = "okay";
0136 };
0137
0138 &mu_m0 {
0139 status = "okay";
0140 };
0141
0142 &mu1_m0 {
0143 status = "okay";
0144 };
0145
0146 &scu_key {
0147 status = "okay";
0148 };
0149
0150 &thermal_zones {
0151 pmic-thermal0 {
0152 polling-delay-passive = <250>;
0153 polling-delay = <2000>;
0154 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
0155
0156 trips {
0157 pmic_alert0: trip0 {
0158 temperature = <110000>;
0159 hysteresis = <2000>;
0160 type = "passive";
0161 };
0162
0163 pmic_crit0: trip1 {
0164 temperature = <125000>;
0165 hysteresis = <2000>;
0166 type = "critical";
0167 };
0168 };
0169
0170 cooling-maps {
0171 map0 {
0172 trip = <&pmic_alert0>;
0173 cooling-device =
0174 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0175 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0176 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0177 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0178 };
0179 };
0180 };
0181 };
0182
0183 &usdhc1 {
0184 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
0185 assigned-clock-rates = <200000000>;
0186 pinctrl-names = "default";
0187 pinctrl-0 = <&pinctrl_usdhc1>;
0188 bus-width = <8>;
0189 no-sd;
0190 no-sdio;
0191 non-removable;
0192 status = "okay";
0193 };
0194
0195 &usdhc2 {
0196 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
0197 assigned-clock-rates = <200000000>;
0198 pinctrl-names = "default";
0199 pinctrl-0 = <&pinctrl_usdhc2>;
0200 bus-width = <4>;
0201 vmmc-supply = <®_usdhc2_vmmc>;
0202 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
0203 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
0204 status = "okay";
0205 };
0206
0207 &vpu {
0208 compatible = "nxp,imx8qxp-vpu";
0209 status = "okay";
0210 };
0211
0212 &vpu_core0 {
0213 reg = <0x2d040000 0x10000>;
0214 memory-region = <&decoder_boot>, <&decoder_rpc>;
0215 status = "okay";
0216 };
0217
0218 &vpu_core1 {
0219 reg = <0x2d050000 0x10000>;
0220 memory-region = <&encoder_boot>, <&encoder_rpc>;
0221 status = "okay";
0222 };
0223
0224 &iomuxc {
0225 pinctrl_fec1: fec1grp {
0226 fsl,pins = <
0227 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
0228 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
0229 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
0230 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
0231 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
0232 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
0233 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
0234 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
0235 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
0236 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
0237 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
0238 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
0239 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
0240 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
0241 >;
0242 };
0243
0244 pinctrl_ioexp_rst: ioexprstgrp {
0245 fsl,pins = <
0246 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
0247 >;
0248 };
0249
0250 pinctrl_isl29023: isl29023grp {
0251 fsl,pins = <
0252 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021
0253 >;
0254 };
0255
0256 pinctrl_lpi2c1: lpi2c1grp {
0257 fsl,pins = <
0258 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
0259 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
0260 >;
0261 };
0262
0263 pinctrl_lpuart0: lpuart0grp {
0264 fsl,pins = <
0265 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
0266 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
0267 >;
0268 };
0269
0270 pinctrl_usdhc1: usdhc1grp {
0271 fsl,pins = <
0272 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
0273 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
0274 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
0275 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
0276 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
0277 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
0278 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
0279 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
0280 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
0281 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
0282 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
0283 >;
0284 };
0285
0286 pinctrl_usdhc2: usdhc2grp {
0287 fsl,pins = <
0288 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
0289 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
0290 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
0291 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
0292 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
0293 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
0294 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
0295 >;
0296 };
0297 };
