0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2018-2019 NXP
0004 * Dong Aisheng <aisheng.dong@nxp.com>
0005 */
0006
0007 #include <dt-bindings/clock/imx8-lpcg.h>
0008 #include <dt-bindings/firmware/imx/rsrc.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/pinctrl/pads-imx8qm.h>
0012
0013 / {
0014 interrupt-parent = <&gic>;
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 aliases {
0019 mmc0 = &usdhc1;
0020 mmc1 = &usdhc2;
0021 mmc2 = &usdhc3;
0022 serial0 = &lpuart0;
0023 serial1 = &lpuart1;
0024 serial2 = &lpuart2;
0025 serial3 = &lpuart3;
0026 };
0027
0028 cpus {
0029 #address-cells = <2>;
0030 #size-cells = <0>;
0031
0032 cpu-map {
0033 cluster0 {
0034 core0 {
0035 cpu = <&A53_0>;
0036 };
0037 core1 {
0038 cpu = <&A53_1>;
0039 };
0040 core2 {
0041 cpu = <&A53_2>;
0042 };
0043 core3 {
0044 cpu = <&A53_3>;
0045 };
0046 };
0047
0048 cluster1 {
0049 core0 {
0050 cpu = <&A72_0>;
0051 };
0052 core1 {
0053 cpu = <&A72_1>;
0054 };
0055 };
0056 };
0057
0058 A53_0: cpu@0 {
0059 device_type = "cpu";
0060 compatible = "arm,cortex-a53";
0061 reg = <0x0 0x0>;
0062 enable-method = "psci";
0063 i-cache-size = <0x8000>;
0064 i-cache-line-size = <64>;
0065 i-cache-sets = <256>;
0066 d-cache-size = <0x8000>;
0067 d-cache-line-size = <64>;
0068 d-cache-sets = <128>;
0069 next-level-cache = <&A53_L2>;
0070 };
0071
0072 A53_1: cpu@1 {
0073 device_type = "cpu";
0074 compatible = "arm,cortex-a53";
0075 reg = <0x0 0x1>;
0076 enable-method = "psci";
0077 i-cache-size = <0x8000>;
0078 i-cache-line-size = <64>;
0079 i-cache-sets = <256>;
0080 d-cache-size = <0x8000>;
0081 d-cache-line-size = <64>;
0082 d-cache-sets = <128>;
0083 next-level-cache = <&A53_L2>;
0084 };
0085
0086 A53_2: cpu@2 {
0087 device_type = "cpu";
0088 compatible = "arm,cortex-a53";
0089 reg = <0x0 0x2>;
0090 enable-method = "psci";
0091 i-cache-size = <0x8000>;
0092 i-cache-line-size = <64>;
0093 i-cache-sets = <256>;
0094 d-cache-size = <0x8000>;
0095 d-cache-line-size = <64>;
0096 d-cache-sets = <128>;
0097 next-level-cache = <&A53_L2>;
0098 };
0099
0100 A53_3: cpu@3 {
0101 device_type = "cpu";
0102 compatible = "arm,cortex-a53";
0103 reg = <0x0 0x3>;
0104 enable-method = "psci";
0105 i-cache-size = <0x8000>;
0106 i-cache-line-size = <64>;
0107 i-cache-sets = <256>;
0108 d-cache-size = <0x8000>;
0109 d-cache-line-size = <64>;
0110 d-cache-sets = <128>;
0111 next-level-cache = <&A53_L2>;
0112 };
0113
0114 A72_0: cpu@100 {
0115 device_type = "cpu";
0116 compatible = "arm,cortex-a72";
0117 reg = <0x0 0x100>;
0118 enable-method = "psci";
0119 i-cache-size = <0xC000>;
0120 i-cache-line-size = <64>;
0121 i-cache-sets = <256>;
0122 d-cache-size = <0x8000>;
0123 d-cache-line-size = <64>;
0124 d-cache-sets = <256>;
0125 next-level-cache = <&A72_L2>;
0126 };
0127
0128 A72_1: cpu@101 {
0129 device_type = "cpu";
0130 compatible = "arm,cortex-a72";
0131 reg = <0x0 0x101>;
0132 enable-method = "psci";
0133 next-level-cache = <&A72_L2>;
0134 };
0135
0136 A53_L2: l2-cache0 {
0137 compatible = "cache";
0138 cache-level = <2>;
0139 cache-size = <0x100000>;
0140 cache-line-size = <64>;
0141 cache-sets = <1024>;
0142 };
0143
0144 A72_L2: l2-cache1 {
0145 compatible = "cache";
0146 cache-level = <2>;
0147 cache-size = <0x100000>;
0148 cache-line-size = <64>;
0149 cache-sets = <1024>;
0150 };
0151 };
0152
0153 gic: interrupt-controller@51a00000 {
0154 compatible = "arm,gic-v3";
0155 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
0156 <0x0 0x51b00000 0 0xC0000>, /* GICR */
0157 <0x0 0x52000000 0 0x2000>, /* GICC */
0158 <0x0 0x52010000 0 0x1000>, /* GICH */
0159 <0x0 0x52020000 0 0x20000>; /* GICV */
0160 #interrupt-cells = <3>;
0161 interrupt-controller;
0162 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
0163 interrupt-parent = <&gic>;
0164 };
0165
0166 pmu {
0167 compatible = "arm,armv8-pmuv3";
0168 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0169 };
0170
0171 psci {
0172 compatible = "arm,psci-1.0";
0173 method = "smc";
0174 };
0175
0176 timer {
0177 compatible = "arm,armv8-timer";
0178 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
0179 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
0180 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
0181 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
0182 };
0183
0184 system-controller {
0185 compatible = "fsl,imx-scu";
0186 mbox-names = "tx0",
0187 "rx0",
0188 "gip3";
0189 mboxes = <&lsio_mu1 0 0
0190 &lsio_mu1 1 0
0191 &lsio_mu1 3 3>;
0192
0193 pd: power-controller {
0194 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
0195 #power-domain-cells = <1>;
0196 };
0197
0198 clk: clock-controller {
0199 compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
0200 #clock-cells = <2>;
0201 };
0202
0203 iomuxc: pinctrl {
0204 compatible = "fsl,imx8qm-iomuxc";
0205 };
0206
0207 rtc: rtc {
0208 compatible = "fsl,imx8qxp-sc-rtc";
0209 };
0210 };
0211
0212 /* sorted in register address */
0213 #include "imx8-ss-img.dtsi"
0214 #include "imx8-ss-dma.dtsi"
0215 #include "imx8-ss-conn.dtsi"
0216 #include "imx8-ss-lsio.dtsi"
0217 };
0218
0219 #include "imx8qm-ss-img.dtsi"
0220 #include "imx8qm-ss-dma.dtsi"
0221 #include "imx8qm-ss-conn.dtsi"
0222 #include "imx8qm-ss-lsio.dtsi"
