0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2018-2019 NXP
0004 * Dong Aisheng <aisheng.dong@nxp.com>
0005 */
0006
0007 &dma_subsys {
0008 uart4_lpcg: clock-controller@5a4a0000 {
0009 compatible = "fsl,imx8qxp-lpcg";
0010 reg = <0x5a4a0000 0x10000>;
0011 #clock-cells = <1>;
0012 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
0013 <&dma_ipg_clk>;
0014 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
0015 clock-output-names = "uart4_lpcg_baud_clk",
0016 "uart4_lpcg_ipg_clk";
0017 power-domains = <&pd IMX_SC_R_UART_4>;
0018 };
0019 };
0020
0021 &lpuart0 {
0022 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
0023 };
0024
0025 &lpuart1 {
0026 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
0027 };
0028
0029 &lpuart2 {
0030 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
0031 };
0032
0033 &lpuart3 {
0034 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
0035 };
0036
0037 &i2c0 {
0038 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
0039 };
0040
0041 &i2c1 {
0042 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
0043 };
0044
0045 &i2c2 {
0046 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
0047 };
0048
0049 &i2c3 {
0050 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
0051 };
