0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2018-2019 NXP
0004 * Dong Aisheng <aisheng.dong@nxp.com>
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "imx8qm.dtsi"
0010
0011 / {
0012 model = "Freescale i.MX8QM MEK";
0013 compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
0014
0015 chosen {
0016 stdout-path = &lpuart0;
0017 };
0018
0019 cpus {
0020 /delete-node/ cpu-map;
0021 /delete-node/ cpu@100;
0022 /delete-node/ cpu@101;
0023 };
0024
0025 memory@80000000 {
0026 device_type = "memory";
0027 reg = <0x00000000 0x80000000 0 0x40000000>;
0028 };
0029
0030 reg_usdhc2_vmmc: usdhc2-vmmc {
0031 compatible = "regulator-fixed";
0032 regulator-name = "SD1_SPWR";
0033 regulator-min-microvolt = <3000000>;
0034 regulator-max-microvolt = <3000000>;
0035 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
0036 enable-active-high;
0037 };
0038 };
0039
0040 &lpuart0 {
0041 pinctrl-names = "default";
0042 pinctrl-0 = <&pinctrl_lpuart0>;
0043 status = "okay";
0044 };
0045
0046 &fec1 {
0047 pinctrl-names = "default";
0048 pinctrl-0 = <&pinctrl_fec1>;
0049 phy-mode = "rgmii-id";
0050 phy-handle = <ðphy0>;
0051 fsl,magic-packet;
0052 status = "okay";
0053
0054 mdio {
0055 #address-cells = <1>;
0056 #size-cells = <0>;
0057
0058 ethphy0: ethernet-phy@0 {
0059 compatible = "ethernet-phy-ieee802.3-c22";
0060 reg = <0>;
0061 };
0062
0063 ethphy1: ethernet-phy@1 {
0064 compatible = "ethernet-phy-ieee802.3-c22";
0065 reg = <1>;
0066 };
0067 };
0068 };
0069
0070 &usdhc1 {
0071 pinctrl-names = "default";
0072 pinctrl-0 = <&pinctrl_usdhc1>;
0073 bus-width = <8>;
0074 no-sd;
0075 no-sdio;
0076 non-removable;
0077 status = "okay";
0078 };
0079
0080 &usdhc2 {
0081 pinctrl-names = "default";
0082 pinctrl-0 = <&pinctrl_usdhc2>;
0083 bus-width = <4>;
0084 vmmc-supply = <®_usdhc2_vmmc>;
0085 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
0086 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
0087 status = "okay";
0088 };
0089
0090 &iomuxc {
0091 pinctrl_fec1: fec1grp {
0092 fsl,pins = <
0093 IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
0094 IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
0095 IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
0096 IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
0097 IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
0098 IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
0099 IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
0100 IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
0101 IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
0102 IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
0103 IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
0104 IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
0105 IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
0106 IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
0107 >;
0108 };
0109
0110 pinctrl_lpuart0: lpuart0grp {
0111 fsl,pins = <
0112 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
0113 IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
0114 >;
0115 };
0116
0117 pinctrl_usdhc1: usdhc1grp {
0118 fsl,pins = <
0119 IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
0120 IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
0121 IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
0122 IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
0123 IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
0124 IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
0125 IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
0126 IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
0127 IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
0128 IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
0129 IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
0130 >;
0131 };
0132
0133 pinctrl_usdhc2: usdhc2grp {
0134 fsl,pins = <
0135 IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
0136 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
0137 IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
0138 IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
0139 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
0140 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
0141 IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
0142 >;
0143 };
0144 };
