0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2017 NXP
0004 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
0005 */
0006
0007 #include <dt-bindings/clock/imx8mq-clock.h>
0008 #include <dt-bindings/power/imx8mq-power.h>
0009 #include <dt-bindings/reset/imx8mq-reset.h>
0010 #include <dt-bindings/gpio/gpio.h>
0011 #include "dt-bindings/input/input.h"
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013 #include <dt-bindings/thermal/thermal.h>
0014 #include <dt-bindings/interconnect/imx8mq.h>
0015 #include "imx8mq-pinfunc.h"
0016
0017 / {
0018 interrupt-parent = <&gpc>;
0019
0020 #address-cells = <2>;
0021 #size-cells = <2>;
0022
0023 aliases {
0024 ethernet0 = &fec1;
0025 gpio0 = &gpio1;
0026 gpio1 = &gpio2;
0027 gpio2 = &gpio3;
0028 gpio3 = &gpio4;
0029 gpio4 = &gpio5;
0030 i2c0 = &i2c1;
0031 i2c1 = &i2c2;
0032 i2c2 = &i2c3;
0033 i2c3 = &i2c4;
0034 mmc0 = &usdhc1;
0035 mmc1 = &usdhc2;
0036 serial0 = &uart1;
0037 serial1 = &uart2;
0038 serial2 = &uart3;
0039 serial3 = &uart4;
0040 spi0 = &ecspi1;
0041 spi1 = &ecspi2;
0042 spi2 = &ecspi3;
0043 };
0044
0045 ckil: clock-ckil {
0046 compatible = "fixed-clock";
0047 #clock-cells = <0>;
0048 clock-frequency = <32768>;
0049 clock-output-names = "ckil";
0050 };
0051
0052 osc_25m: clock-osc-25m {
0053 compatible = "fixed-clock";
0054 #clock-cells = <0>;
0055 clock-frequency = <25000000>;
0056 clock-output-names = "osc_25m";
0057 };
0058
0059 osc_27m: clock-osc-27m {
0060 compatible = "fixed-clock";
0061 #clock-cells = <0>;
0062 clock-frequency = <27000000>;
0063 clock-output-names = "osc_27m";
0064 };
0065
0066 hdmi_phy_27m: clock-hdmi-phy-27m {
0067 compatible = "fixed-clock";
0068 #clock-cells = <0>;
0069 clock-frequency = <27000000>;
0070 clock-output-names = "hdmi_phy_27m";
0071 };
0072
0073 clk_ext1: clock-ext1 {
0074 compatible = "fixed-clock";
0075 #clock-cells = <0>;
0076 clock-frequency = <133000000>;
0077 clock-output-names = "clk_ext1";
0078 };
0079
0080 clk_ext2: clock-ext2 {
0081 compatible = "fixed-clock";
0082 #clock-cells = <0>;
0083 clock-frequency = <133000000>;
0084 clock-output-names = "clk_ext2";
0085 };
0086
0087 clk_ext3: clock-ext3 {
0088 compatible = "fixed-clock";
0089 #clock-cells = <0>;
0090 clock-frequency = <133000000>;
0091 clock-output-names = "clk_ext3";
0092 };
0093
0094 clk_ext4: clock-ext4 {
0095 compatible = "fixed-clock";
0096 #clock-cells = <0>;
0097 clock-frequency = <133000000>;
0098 clock-output-names = "clk_ext4";
0099 };
0100
0101 cpus {
0102 #address-cells = <1>;
0103 #size-cells = <0>;
0104
0105 A53_0: cpu@0 {
0106 device_type = "cpu";
0107 compatible = "arm,cortex-a53";
0108 reg = <0x0>;
0109 clock-latency = <61036>; /* two CLK32 periods */
0110 clocks = <&clk IMX8MQ_CLK_ARM>;
0111 enable-method = "psci";
0112 i-cache-size = <0x8000>;
0113 i-cache-line-size = <64>;
0114 i-cache-sets = <256>;
0115 d-cache-size = <0x8000>;
0116 d-cache-line-size = <64>;
0117 d-cache-sets = <128>;
0118 next-level-cache = <&A53_L2>;
0119 operating-points-v2 = <&a53_opp_table>;
0120 #cooling-cells = <2>;
0121 nvmem-cells = <&cpu_speed_grade>;
0122 nvmem-cell-names = "speed_grade";
0123 };
0124
0125 A53_1: cpu@1 {
0126 device_type = "cpu";
0127 compatible = "arm,cortex-a53";
0128 reg = <0x1>;
0129 clock-latency = <61036>; /* two CLK32 periods */
0130 clocks = <&clk IMX8MQ_CLK_ARM>;
0131 enable-method = "psci";
0132 i-cache-size = <0x8000>;
0133 i-cache-line-size = <64>;
0134 i-cache-sets = <256>;
0135 d-cache-size = <0x8000>;
0136 d-cache-line-size = <64>;
0137 d-cache-sets = <128>;
0138 next-level-cache = <&A53_L2>;
0139 operating-points-v2 = <&a53_opp_table>;
0140 #cooling-cells = <2>;
0141 };
0142
0143 A53_2: cpu@2 {
0144 device_type = "cpu";
0145 compatible = "arm,cortex-a53";
0146 reg = <0x2>;
0147 clock-latency = <61036>; /* two CLK32 periods */
0148 clocks = <&clk IMX8MQ_CLK_ARM>;
0149 enable-method = "psci";
0150 i-cache-size = <0x8000>;
0151 i-cache-line-size = <64>;
0152 i-cache-sets = <256>;
0153 d-cache-size = <0x8000>;
0154 d-cache-line-size = <64>;
0155 d-cache-sets = <128>;
0156 next-level-cache = <&A53_L2>;
0157 operating-points-v2 = <&a53_opp_table>;
0158 #cooling-cells = <2>;
0159 };
0160
0161 A53_3: cpu@3 {
0162 device_type = "cpu";
0163 compatible = "arm,cortex-a53";
0164 reg = <0x3>;
0165 clock-latency = <61036>; /* two CLK32 periods */
0166 clocks = <&clk IMX8MQ_CLK_ARM>;
0167 enable-method = "psci";
0168 i-cache-size = <0x8000>;
0169 i-cache-line-size = <64>;
0170 i-cache-sets = <256>;
0171 d-cache-size = <0x8000>;
0172 d-cache-line-size = <64>;
0173 d-cache-sets = <128>;
0174 next-level-cache = <&A53_L2>;
0175 operating-points-v2 = <&a53_opp_table>;
0176 #cooling-cells = <2>;
0177 };
0178
0179 A53_L2: l2-cache0 {
0180 compatible = "cache";
0181 cache-level = <2>;
0182 cache-size = <0x100000>;
0183 cache-line-size = <64>;
0184 cache-sets = <1024>;
0185 };
0186 };
0187
0188 a53_opp_table: opp-table {
0189 compatible = "operating-points-v2";
0190 opp-shared;
0191
0192 opp-800000000 {
0193 opp-hz = /bits/ 64 <800000000>;
0194 opp-microvolt = <900000>;
0195 /* Industrial only */
0196 opp-supported-hw = <0xf>, <0x4>;
0197 clock-latency-ns = <150000>;
0198 opp-suspend;
0199 };
0200
0201 opp-1000000000 {
0202 opp-hz = /bits/ 64 <1000000000>;
0203 opp-microvolt = <900000>;
0204 /* Consumer only */
0205 opp-supported-hw = <0xe>, <0x3>;
0206 clock-latency-ns = <150000>;
0207 opp-suspend;
0208 };
0209
0210 opp-1300000000 {
0211 opp-hz = /bits/ 64 <1300000000>;
0212 opp-microvolt = <1000000>;
0213 opp-supported-hw = <0xc>, <0x4>;
0214 clock-latency-ns = <150000>;
0215 opp-suspend;
0216 };
0217
0218 opp-1500000000 {
0219 opp-hz = /bits/ 64 <1500000000>;
0220 opp-microvolt = <1000000>;
0221 opp-supported-hw = <0x8>, <0x3>;
0222 clock-latency-ns = <150000>;
0223 opp-suspend;
0224 };
0225 };
0226
0227 pmu {
0228 compatible = "arm,cortex-a53-pmu";
0229 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
0230 interrupt-parent = <&gic>;
0231 };
0232
0233 psci {
0234 compatible = "arm,psci-1.0";
0235 method = "smc";
0236 };
0237
0238 thermal-zones {
0239 cpu_thermal: cpu-thermal {
0240 polling-delay-passive = <250>;
0241 polling-delay = <2000>;
0242 thermal-sensors = <&tmu 0>;
0243
0244 trips {
0245 cpu_alert: cpu-alert {
0246 temperature = <80000>;
0247 hysteresis = <2000>;
0248 type = "passive";
0249 };
0250
0251 cpu-crit {
0252 temperature = <90000>;
0253 hysteresis = <2000>;
0254 type = "critical";
0255 };
0256 };
0257
0258 cooling-maps {
0259 map0 {
0260 trip = <&cpu_alert>;
0261 cooling-device =
0262 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0263 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0264 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0265 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0266 };
0267 };
0268 };
0269
0270 gpu-thermal {
0271 polling-delay-passive = <250>;
0272 polling-delay = <2000>;
0273 thermal-sensors = <&tmu 1>;
0274
0275 trips {
0276 gpu_alert: gpu-alert {
0277 temperature = <80000>;
0278 hysteresis = <2000>;
0279 type = "passive";
0280 };
0281
0282 gpu-crit {
0283 temperature = <90000>;
0284 hysteresis = <2000>;
0285 type = "critical";
0286 };
0287 };
0288
0289 cooling-maps {
0290 map0 {
0291 trip = <&gpu_alert>;
0292 cooling-device =
0293 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0294 };
0295 };
0296 };
0297
0298 vpu-thermal {
0299 polling-delay-passive = <250>;
0300 polling-delay = <2000>;
0301 thermal-sensors = <&tmu 2>;
0302
0303 trips {
0304 vpu-crit {
0305 temperature = <90000>;
0306 hysteresis = <2000>;
0307 type = "critical";
0308 };
0309 };
0310 };
0311 };
0312
0313 timer {
0314 compatible = "arm,armv8-timer";
0315 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
0316 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
0317 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
0318 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
0319 interrupt-parent = <&gic>;
0320 arm,no-tick-in-suspend;
0321 };
0322
0323 soc: soc@0 {
0324 compatible = "fsl,imx8mq-soc", "simple-bus";
0325 #address-cells = <1>;
0326 #size-cells = <1>;
0327 ranges = <0x0 0x0 0x0 0x3e000000>;
0328 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
0329 nvmem-cells = <&imx8mq_uid>;
0330 nvmem-cell-names = "soc_unique_id";
0331
0332 aips1: bus@30000000 { /* AIPS1 */
0333 compatible = "fsl,aips-bus", "simple-bus";
0334 reg = <0x30000000 0x400000>;
0335 #address-cells = <1>;
0336 #size-cells = <1>;
0337 ranges = <0x30000000 0x30000000 0x400000>;
0338
0339 sai1: sai@30010000 {
0340 #sound-dai-cells = <0>;
0341 compatible = "fsl,imx8mq-sai";
0342 reg = <0x30010000 0x10000>;
0343 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0344 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
0345 <&clk IMX8MQ_CLK_SAI1_ROOT>,
0346 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
0347 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0348 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
0349 dma-names = "rx", "tx";
0350 status = "disabled";
0351 };
0352
0353 sai6: sai@30030000 {
0354 #sound-dai-cells = <0>;
0355 compatible = "fsl,imx8mq-sai";
0356 reg = <0x30030000 0x10000>;
0357 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0358 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
0359 <&clk IMX8MQ_CLK_SAI6_ROOT>,
0360 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
0361 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0362 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
0363 dma-names = "rx", "tx";
0364 status = "disabled";
0365 };
0366
0367 sai5: sai@30040000 {
0368 #sound-dai-cells = <0>;
0369 compatible = "fsl,imx8mq-sai";
0370 reg = <0x30040000 0x10000>;
0371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0372 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
0373 <&clk IMX8MQ_CLK_SAI5_ROOT>,
0374 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
0375 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0376 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
0377 dma-names = "rx", "tx";
0378 status = "disabled";
0379 };
0380
0381 sai4: sai@30050000 {
0382 #sound-dai-cells = <0>;
0383 compatible = "fsl,imx8mq-sai";
0384 reg = <0x30050000 0x10000>;
0385 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0386 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
0387 <&clk IMX8MQ_CLK_SAI4_ROOT>,
0388 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
0389 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0390 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
0391 dma-names = "rx", "tx";
0392 status = "disabled";
0393 };
0394
0395 gpio1: gpio@30200000 {
0396 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
0397 reg = <0x30200000 0x10000>;
0398 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
0399 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0400 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
0401 gpio-controller;
0402 #gpio-cells = <2>;
0403 interrupt-controller;
0404 #interrupt-cells = <2>;
0405 gpio-ranges = <&iomuxc 0 10 30>;
0406 };
0407
0408 gpio2: gpio@30210000 {
0409 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
0410 reg = <0x30210000 0x10000>;
0411 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
0412 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0413 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
0414 gpio-controller;
0415 #gpio-cells = <2>;
0416 interrupt-controller;
0417 #interrupt-cells = <2>;
0418 gpio-ranges = <&iomuxc 0 40 21>;
0419 };
0420
0421 gpio3: gpio@30220000 {
0422 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
0423 reg = <0x30220000 0x10000>;
0424 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0425 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0426 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
0427 gpio-controller;
0428 #gpio-cells = <2>;
0429 interrupt-controller;
0430 #interrupt-cells = <2>;
0431 gpio-ranges = <&iomuxc 0 61 26>;
0432 };
0433
0434 gpio4: gpio@30230000 {
0435 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
0436 reg = <0x30230000 0x10000>;
0437 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0438 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0439 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
0440 gpio-controller;
0441 #gpio-cells = <2>;
0442 interrupt-controller;
0443 #interrupt-cells = <2>;
0444 gpio-ranges = <&iomuxc 0 87 32>;
0445 };
0446
0447 gpio5: gpio@30240000 {
0448 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
0449 reg = <0x30240000 0x10000>;
0450 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0451 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0452 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
0453 gpio-controller;
0454 #gpio-cells = <2>;
0455 interrupt-controller;
0456 #interrupt-cells = <2>;
0457 gpio-ranges = <&iomuxc 0 119 30>;
0458 };
0459
0460 tmu: tmu@30260000 {
0461 compatible = "fsl,imx8mq-tmu";
0462 reg = <0x30260000 0x10000>;
0463 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0464 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
0465 little-endian;
0466 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
0467 fsl,tmu-calibration = <0x00000000 0x00000023>,
0468 <0x00000001 0x00000029>,
0469 <0x00000002 0x0000002f>,
0470 <0x00000003 0x00000035>,
0471 <0x00000004 0x0000003d>,
0472 <0x00000005 0x00000043>,
0473 <0x00000006 0x0000004b>,
0474 <0x00000007 0x00000051>,
0475 <0x00000008 0x00000057>,
0476 <0x00000009 0x0000005f>,
0477 <0x0000000a 0x00000067>,
0478 <0x0000000b 0x0000006f>,
0479
0480 <0x00010000 0x0000001b>,
0481 <0x00010001 0x00000023>,
0482 <0x00010002 0x0000002b>,
0483 <0x00010003 0x00000033>,
0484 <0x00010004 0x0000003b>,
0485 <0x00010005 0x00000043>,
0486 <0x00010006 0x0000004b>,
0487 <0x00010007 0x00000055>,
0488 <0x00010008 0x0000005d>,
0489 <0x00010009 0x00000067>,
0490 <0x0001000a 0x00000070>,
0491
0492 <0x00020000 0x00000017>,
0493 <0x00020001 0x00000023>,
0494 <0x00020002 0x0000002d>,
0495 <0x00020003 0x00000037>,
0496 <0x00020004 0x00000041>,
0497 <0x00020005 0x0000004b>,
0498 <0x00020006 0x00000057>,
0499 <0x00020007 0x00000063>,
0500 <0x00020008 0x0000006f>,
0501
0502 <0x00030000 0x00000015>,
0503 <0x00030001 0x00000021>,
0504 <0x00030002 0x0000002d>,
0505 <0x00030003 0x00000039>,
0506 <0x00030004 0x00000045>,
0507 <0x00030005 0x00000053>,
0508 <0x00030006 0x0000005f>,
0509 <0x00030007 0x00000071>;
0510 #thermal-sensor-cells = <1>;
0511 };
0512
0513 wdog1: watchdog@30280000 {
0514 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
0515 reg = <0x30280000 0x10000>;
0516 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0517 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
0518 status = "disabled";
0519 };
0520
0521 wdog2: watchdog@30290000 {
0522 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
0523 reg = <0x30290000 0x10000>;
0524 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0525 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
0526 status = "disabled";
0527 };
0528
0529 wdog3: watchdog@302a0000 {
0530 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
0531 reg = <0x302a0000 0x10000>;
0532 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0533 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
0534 status = "disabled";
0535 };
0536
0537 sdma2: sdma@302c0000 {
0538 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
0539 reg = <0x302c0000 0x10000>;
0540 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0541 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
0542 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
0543 clock-names = "ipg", "ahb";
0544 #dma-cells = <3>;
0545 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
0546 };
0547
0548 lcdif: lcd-controller@30320000 {
0549 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
0550 reg = <0x30320000 0x10000>;
0551 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0552 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
0553 clock-names = "pix";
0554 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
0555 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
0556 <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
0557 <&clk IMX8MQ_VIDEO_PLL1>;
0558 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
0559 <&clk IMX8MQ_VIDEO_PLL1>,
0560 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
0561 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
0562 status = "disabled";
0563
0564 port {
0565 lcdif_mipi_dsi: endpoint {
0566 remote-endpoint = <&mipi_dsi_lcdif_in>;
0567 };
0568 };
0569 };
0570
0571 iomuxc: pinctrl@30330000 {
0572 compatible = "fsl,imx8mq-iomuxc";
0573 reg = <0x30330000 0x10000>;
0574 };
0575
0576 iomuxc_gpr: syscon@30340000 {
0577 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
0578 "syscon", "simple-mfd";
0579 reg = <0x30340000 0x10000>;
0580
0581 mux: mux-controller {
0582 compatible = "mmio-mux";
0583 #mux-control-cells = <1>;
0584 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
0585 };
0586 };
0587
0588 ocotp: efuse@30350000 {
0589 compatible = "fsl,imx8mq-ocotp", "syscon";
0590 reg = <0x30350000 0x10000>;
0591 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
0592 #address-cells = <1>;
0593 #size-cells = <1>;
0594
0595 imx8mq_uid: soc-uid@410 {
0596 reg = <0x4 0x8>;
0597 };
0598
0599 cpu_speed_grade: speed-grade@10 {
0600 reg = <0x10 4>;
0601 };
0602
0603 fec_mac_address: mac-address@90 {
0604 reg = <0x90 6>;
0605 };
0606 };
0607
0608 anatop: syscon@30360000 {
0609 compatible = "fsl,imx8mq-anatop", "syscon";
0610 reg = <0x30360000 0x10000>;
0611 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0612 };
0613
0614 snvs: snvs@30370000 {
0615 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
0616 reg = <0x30370000 0x10000>;
0617
0618 snvs_rtc: snvs-rtc-lp{
0619 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0620 regmap =<&snvs>;
0621 offset = <0x34>;
0622 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0623 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0624 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
0625 clock-names = "snvs-rtc";
0626 };
0627
0628 snvs_pwrkey: snvs-powerkey {
0629 compatible = "fsl,sec-v4.0-pwrkey";
0630 regmap = <&snvs>;
0631 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0632 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
0633 clock-names = "snvs-pwrkey";
0634 linux,keycode = <KEY_POWER>;
0635 wakeup-source;
0636 status = "disabled";
0637 };
0638 };
0639
0640 clk: clock-controller@30380000 {
0641 compatible = "fsl,imx8mq-ccm";
0642 reg = <0x30380000 0x10000>;
0643 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
0644 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0645 #clock-cells = <1>;
0646 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
0647 <&clk_ext1>, <&clk_ext2>,
0648 <&clk_ext3>, <&clk_ext4>;
0649 clock-names = "ckil", "osc_25m", "osc_27m",
0650 "clk_ext1", "clk_ext2",
0651 "clk_ext3", "clk_ext4";
0652 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
0653 <&clk IMX8MQ_CLK_A53_CORE>,
0654 <&clk IMX8MQ_CLK_NOC>,
0655 <&clk IMX8MQ_CLK_AUDIO_AHB>,
0656 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,
0657 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,
0658 <&clk IMX8MQ_AUDIO_PLL1>,
0659 <&clk IMX8MQ_AUDIO_PLL2>;
0660 assigned-clock-rates = <0>, <0>,
0661 <800000000>,
0662 <0>,
0663 <0>,
0664 <0>,
0665 <786432000>,
0666 <722534400>;
0667 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
0668 <&clk IMX8MQ_ARM_PLL_OUT>,
0669 <0>,
0670 <&clk IMX8MQ_SYS2_PLL_500M>,
0671 <&clk IMX8MQ_AUDIO_PLL1>,
0672 <&clk IMX8MQ_AUDIO_PLL2>;
0673 };
0674
0675 src: reset-controller@30390000 {
0676 compatible = "fsl,imx8mq-src", "syscon";
0677 reg = <0x30390000 0x10000>;
0678 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0679 #reset-cells = <1>;
0680 };
0681
0682 gpc: gpc@303a0000 {
0683 compatible = "fsl,imx8mq-gpc";
0684 reg = <0x303a0000 0x10000>;
0685 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0686 interrupt-parent = <&gic>;
0687 interrupt-controller;
0688 #interrupt-cells = <3>;
0689
0690 pgc {
0691 #address-cells = <1>;
0692 #size-cells = <0>;
0693
0694 pgc_mipi: power-domain@0 {
0695 #power-domain-cells = <0>;
0696 reg = <IMX8M_POWER_DOMAIN_MIPI>;
0697 };
0698
0699 /*
0700 * As per comment in ATF source code:
0701 *
0702 * PCIE1 and PCIE2 share the
0703 * same reset signal, if we
0704 * power down PCIE2, PCIE1
0705 * will be held in reset too.
0706 *
0707 * So instead of creating two
0708 * separate power domains for
0709 * PCIE1 and PCIE2 we create a
0710 * link between both and use
0711 * it as a shared PCIE power
0712 * domain.
0713 */
0714 pgc_pcie: power-domain@1 {
0715 #power-domain-cells = <0>;
0716 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
0717 power-domains = <&pgc_pcie2>;
0718 };
0719
0720 pgc_otg1: power-domain@2 {
0721 #power-domain-cells = <0>;
0722 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
0723 };
0724
0725 pgc_otg2: power-domain@3 {
0726 #power-domain-cells = <0>;
0727 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
0728 };
0729
0730 pgc_ddr1: power-domain@4 {
0731 #power-domain-cells = <0>;
0732 reg = <IMX8M_POWER_DOMAIN_DDR1>;
0733 };
0734
0735 pgc_gpu: power-domain@5 {
0736 #power-domain-cells = <0>;
0737 reg = <IMX8M_POWER_DOMAIN_GPU>;
0738 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
0739 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
0740 <&clk IMX8MQ_CLK_GPU_AXI>,
0741 <&clk IMX8MQ_CLK_GPU_AHB>;
0742 };
0743
0744 pgc_vpu: power-domain@6 {
0745 #power-domain-cells = <0>;
0746 reg = <IMX8M_POWER_DOMAIN_VPU>;
0747 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
0748 <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
0749 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
0750 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
0751 <&clk IMX8MQ_CLK_VPU_G2>,
0752 <&clk IMX8MQ_CLK_VPU_BUS>,
0753 <&clk IMX8MQ_VPU_PLL_BYPASS>;
0754 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
0755 <&clk IMX8MQ_VPU_PLL_OUT>,
0756 <&clk IMX8MQ_SYS1_PLL_800M>,
0757 <&clk IMX8MQ_VPU_PLL>;
0758 assigned-clock-rates = <600000000>,
0759 <600000000>,
0760 <800000000>,
0761 <0>;
0762 };
0763
0764 pgc_disp: power-domain@7 {
0765 #power-domain-cells = <0>;
0766 reg = <IMX8M_POWER_DOMAIN_DISP>;
0767 };
0768
0769 pgc_mipi_csi1: power-domain@8 {
0770 #power-domain-cells = <0>;
0771 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
0772 };
0773
0774 pgc_mipi_csi2: power-domain@9 {
0775 #power-domain-cells = <0>;
0776 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
0777 };
0778
0779 pgc_pcie2: power-domain@a {
0780 #power-domain-cells = <0>;
0781 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
0782 };
0783 };
0784 };
0785 };
0786
0787 aips2: bus@30400000 { /* AIPS2 */
0788 compatible = "fsl,aips-bus", "simple-bus";
0789 reg = <0x30400000 0x400000>;
0790 #address-cells = <1>;
0791 #size-cells = <1>;
0792 ranges = <0x30400000 0x30400000 0x400000>;
0793
0794 pwm1: pwm@30660000 {
0795 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
0796 reg = <0x30660000 0x10000>;
0797 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0798 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
0799 <&clk IMX8MQ_CLK_PWM1_ROOT>;
0800 clock-names = "ipg", "per";
0801 #pwm-cells = <3>;
0802 status = "disabled";
0803 };
0804
0805 pwm2: pwm@30670000 {
0806 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
0807 reg = <0x30670000 0x10000>;
0808 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0809 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
0810 <&clk IMX8MQ_CLK_PWM2_ROOT>;
0811 clock-names = "ipg", "per";
0812 #pwm-cells = <3>;
0813 status = "disabled";
0814 };
0815
0816 pwm3: pwm@30680000 {
0817 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
0818 reg = <0x30680000 0x10000>;
0819 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0820 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
0821 <&clk IMX8MQ_CLK_PWM3_ROOT>;
0822 clock-names = "ipg", "per";
0823 #pwm-cells = <3>;
0824 status = "disabled";
0825 };
0826
0827 pwm4: pwm@30690000 {
0828 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
0829 reg = <0x30690000 0x10000>;
0830 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0831 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
0832 <&clk IMX8MQ_CLK_PWM4_ROOT>;
0833 clock-names = "ipg", "per";
0834 #pwm-cells = <3>;
0835 status = "disabled";
0836 };
0837
0838 system_counter: timer@306a0000 {
0839 compatible = "nxp,sysctr-timer";
0840 reg = <0x306a0000 0x20000>;
0841 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0842 clocks = <&osc_25m>;
0843 clock-names = "per";
0844 };
0845 };
0846
0847 aips3: bus@30800000 { /* AIPS3 */
0848 compatible = "fsl,aips-bus", "simple-bus";
0849 reg = <0x30800000 0x400000>;
0850 #address-cells = <1>;
0851 #size-cells = <1>;
0852 ranges = <0x30800000 0x30800000 0x400000>,
0853 <0x08000000 0x08000000 0x10000000>;
0854
0855 spdif1: spdif@30810000 {
0856 compatible = "fsl,imx35-spdif";
0857 reg = <0x30810000 0x10000>;
0858 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0859 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
0860 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
0861 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
0862 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
0863 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
0864 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
0865 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
0866 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
0867 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
0868 <&clk IMX8MQ_CLK_DUMMY>; /* spba */
0869 clock-names = "core", "rxtx0",
0870 "rxtx1", "rxtx2",
0871 "rxtx3", "rxtx4",
0872 "rxtx5", "rxtx6",
0873 "rxtx7", "spba";
0874 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
0875 dma-names = "rx", "tx";
0876 status = "disabled";
0877 };
0878
0879 ecspi1: spi@30820000 {
0880 #address-cells = <1>;
0881 #size-cells = <0>;
0882 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
0883 reg = <0x30820000 0x10000>;
0884 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0885 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
0886 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
0887 clock-names = "ipg", "per";
0888 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
0889 dma-names = "rx", "tx";
0890 status = "disabled";
0891 };
0892
0893 ecspi2: spi@30830000 {
0894 #address-cells = <1>;
0895 #size-cells = <0>;
0896 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
0897 reg = <0x30830000 0x10000>;
0898 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0899 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
0900 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
0901 clock-names = "ipg", "per";
0902 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
0903 dma-names = "rx", "tx";
0904 status = "disabled";
0905 };
0906
0907 ecspi3: spi@30840000 {
0908 #address-cells = <1>;
0909 #size-cells = <0>;
0910 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
0911 reg = <0x30840000 0x10000>;
0912 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0913 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
0914 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
0915 clock-names = "ipg", "per";
0916 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
0917 dma-names = "rx", "tx";
0918 status = "disabled";
0919 };
0920
0921 uart1: serial@30860000 {
0922 compatible = "fsl,imx8mq-uart",
0923 "fsl,imx6q-uart";
0924 reg = <0x30860000 0x10000>;
0925 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0926 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
0927 <&clk IMX8MQ_CLK_UART1_ROOT>;
0928 clock-names = "ipg", "per";
0929 status = "disabled";
0930 };
0931
0932 uart3: serial@30880000 {
0933 compatible = "fsl,imx8mq-uart",
0934 "fsl,imx6q-uart";
0935 reg = <0x30880000 0x10000>;
0936 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0937 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
0938 <&clk IMX8MQ_CLK_UART3_ROOT>;
0939 clock-names = "ipg", "per";
0940 status = "disabled";
0941 };
0942
0943 uart2: serial@30890000 {
0944 compatible = "fsl,imx8mq-uart",
0945 "fsl,imx6q-uart";
0946 reg = <0x30890000 0x10000>;
0947 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0948 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
0949 <&clk IMX8MQ_CLK_UART2_ROOT>;
0950 clock-names = "ipg", "per";
0951 status = "disabled";
0952 };
0953
0954 spdif2: spdif@308a0000 {
0955 compatible = "fsl,imx35-spdif";
0956 reg = <0x308a0000 0x10000>;
0957 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0958 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
0959 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
0960 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
0961 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
0962 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
0963 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
0964 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
0965 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
0966 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
0967 <&clk IMX8MQ_CLK_DUMMY>; /* spba */
0968 clock-names = "core", "rxtx0",
0969 "rxtx1", "rxtx2",
0970 "rxtx3", "rxtx4",
0971 "rxtx5", "rxtx6",
0972 "rxtx7", "spba";
0973 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
0974 dma-names = "rx", "tx";
0975 status = "disabled";
0976 };
0977
0978 sai2: sai@308b0000 {
0979 #sound-dai-cells = <0>;
0980 compatible = "fsl,imx8mq-sai";
0981 reg = <0x308b0000 0x10000>;
0982 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0983 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
0984 <&clk IMX8MQ_CLK_SAI2_ROOT>,
0985 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
0986 clock-names = "bus", "mclk1", "mclk2", "mclk3";
0987 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
0988 dma-names = "rx", "tx";
0989 status = "disabled";
0990 };
0991
0992 sai3: sai@308c0000 {
0993 #sound-dai-cells = <0>;
0994 compatible = "fsl,imx8mq-sai";
0995 reg = <0x308c0000 0x10000>;
0996 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0997 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
0998 <&clk IMX8MQ_CLK_SAI3_ROOT>,
0999 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
1000 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1001 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
1002 dma-names = "rx", "tx";
1003 status = "disabled";
1004 };
1005
1006 crypto: crypto@30900000 {
1007 compatible = "fsl,sec-v4.0";
1008 #address-cells = <1>;
1009 #size-cells = <1>;
1010 reg = <0x30900000 0x40000>;
1011 ranges = <0 0x30900000 0x40000>;
1012 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&clk IMX8MQ_CLK_AHB>,
1014 <&clk IMX8MQ_CLK_IPG_ROOT>;
1015 clock-names = "aclk", "ipg";
1016
1017 sec_jr0: jr@1000 {
1018 compatible = "fsl,sec-v4.0-job-ring";
1019 reg = <0x1000 0x1000>;
1020 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1021 status = "disabled";
1022 };
1023
1024 sec_jr1: jr@2000 {
1025 compatible = "fsl,sec-v4.0-job-ring";
1026 reg = <0x2000 0x1000>;
1027 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1028 };
1029
1030 sec_jr2: jr@3000 {
1031 compatible = "fsl,sec-v4.0-job-ring";
1032 reg = <0x3000 0x1000>;
1033 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1034 };
1035 };
1036
1037 mipi_dsi: mipi-dsi@30a00000 {
1038 compatible = "fsl,imx8mq-nwl-dsi";
1039 reg = <0x30a00000 0x300>;
1040 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
1041 <&clk IMX8MQ_CLK_DSI_AHB>,
1042 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
1043 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1044 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
1045 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
1046 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
1047 <&clk IMX8MQ_CLK_DSI_CORE>,
1048 <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
1049 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1050 <&clk IMX8MQ_SYS1_PLL_266M>;
1051 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1052 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1053 mux-controls = <&mux 0>;
1054 power-domains = <&pgc_mipi>;
1055 phys = <&dphy>;
1056 phy-names = "dphy";
1057 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
1058 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
1059 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
1060 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
1061 reset-names = "byte", "dpi", "esc", "pclk";
1062 status = "disabled";
1063
1064 ports {
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1067
1068 port@0 {
1069 reg = <0>;
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1072 mipi_dsi_lcdif_in: endpoint@0 {
1073 reg = <0>;
1074 remote-endpoint = <&lcdif_mipi_dsi>;
1075 };
1076 };
1077 };
1078 };
1079
1080 dphy: dphy@30a00300 {
1081 compatible = "fsl,imx8mq-mipi-dphy";
1082 reg = <0x30a00300 0x100>;
1083 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
1084 clock-names = "phy_ref";
1085 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1086 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
1087 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1088 <&clk IMX8MQ_VIDEO_PLL1>;
1089 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1090 <&clk IMX8MQ_VIDEO_PLL1>,
1091 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
1092 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1093 #phy-cells = <0>;
1094 power-domains = <&pgc_mipi>;
1095 status = "disabled";
1096 };
1097
1098 i2c1: i2c@30a20000 {
1099 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1100 reg = <0x30a20000 0x10000>;
1101 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1102 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 status = "disabled";
1106 };
1107
1108 i2c2: i2c@30a30000 {
1109 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1110 reg = <0x30a30000 0x10000>;
1111 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1112 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
1113 #address-cells = <1>;
1114 #size-cells = <0>;
1115 status = "disabled";
1116 };
1117
1118 i2c3: i2c@30a40000 {
1119 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1120 reg = <0x30a40000 0x10000>;
1121 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1122 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125 status = "disabled";
1126 };
1127
1128 i2c4: i2c@30a50000 {
1129 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1130 reg = <0x30a50000 0x10000>;
1131 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1135 status = "disabled";
1136 };
1137
1138 uart4: serial@30a60000 {
1139 compatible = "fsl,imx8mq-uart",
1140 "fsl,imx6q-uart";
1141 reg = <0x30a60000 0x10000>;
1142 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
1144 <&clk IMX8MQ_CLK_UART4_ROOT>;
1145 clock-names = "ipg", "per";
1146 status = "disabled";
1147 };
1148
1149 mipi_csi1: csi@30a70000 {
1150 compatible = "fsl,imx8mq-mipi-csi2";
1151 reg = <0x30a70000 0x1000>;
1152 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1153 <&clk IMX8MQ_CLK_CSI1_ESC>,
1154 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
1155 clock-names = "core", "esc", "ui";
1156 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1157 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
1158 <&clk IMX8MQ_CLK_CSI1_ESC>;
1159 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1160 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1161 <&clk IMX8MQ_SYS2_PLL_1000M>,
1162 <&clk IMX8MQ_SYS1_PLL_800M>;
1163 power-domains = <&pgc_mipi_csi1>;
1164 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
1165 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
1166 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
1167 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1168 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
1169 interconnect-names = "dram";
1170 status = "disabled";
1171
1172 ports {
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1175
1176 port@1 {
1177 reg = <1>;
1178
1179 csi1_mipi_ep: endpoint {
1180 remote-endpoint = <&csi1_ep>;
1181 };
1182 };
1183 };
1184 };
1185
1186 csi1: csi@30a90000 {
1187 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1188 reg = <0x30a90000 0x10000>;
1189 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1190 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
1191 clock-names = "mclk";
1192 status = "disabled";
1193
1194 port {
1195 csi1_ep: endpoint {
1196 remote-endpoint = <&csi1_mipi_ep>;
1197 };
1198 };
1199 };
1200
1201 mipi_csi2: csi@30b60000 {
1202 compatible = "fsl,imx8mq-mipi-csi2";
1203 reg = <0x30b60000 0x1000>;
1204 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1205 <&clk IMX8MQ_CLK_CSI2_ESC>,
1206 <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
1207 clock-names = "core", "esc", "ui";
1208 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1209 <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
1210 <&clk IMX8MQ_CLK_CSI2_ESC>;
1211 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1212 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1213 <&clk IMX8MQ_SYS2_PLL_1000M>,
1214 <&clk IMX8MQ_SYS1_PLL_800M>;
1215 power-domains = <&pgc_mipi_csi2>;
1216 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
1217 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
1218 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
1219 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1220 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
1221 interconnect-names = "dram";
1222 status = "disabled";
1223
1224 ports {
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227
1228 port@1 {
1229 reg = <1>;
1230
1231 csi2_mipi_ep: endpoint {
1232 remote-endpoint = <&csi2_ep>;
1233 };
1234 };
1235 };
1236 };
1237
1238 csi2: csi@30b80000 {
1239 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1240 reg = <0x30b80000 0x10000>;
1241 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1242 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
1243 clock-names = "mclk";
1244 status = "disabled";
1245
1246 port {
1247 csi2_ep: endpoint {
1248 remote-endpoint = <&csi2_mipi_ep>;
1249 };
1250 };
1251 };
1252
1253 mu: mailbox@30aa0000 {
1254 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1255 reg = <0x30aa0000 0x10000>;
1256 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1257 clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
1258 #mbox-cells = <2>;
1259 };
1260
1261 usdhc1: mmc@30b40000 {
1262 compatible = "fsl,imx8mq-usdhc",
1263 "fsl,imx7d-usdhc";
1264 reg = <0x30b40000 0x10000>;
1265 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1266 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1267 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1268 <&clk IMX8MQ_CLK_USDHC1_ROOT>;
1269 clock-names = "ipg", "ahb", "per";
1270 fsl,tuning-start-tap = <20>;
1271 fsl,tuning-step = <2>;
1272 bus-width = <4>;
1273 status = "disabled";
1274 };
1275
1276 usdhc2: mmc@30b50000 {
1277 compatible = "fsl,imx8mq-usdhc",
1278 "fsl,imx7d-usdhc";
1279 reg = <0x30b50000 0x10000>;
1280 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1282 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1283 <&clk IMX8MQ_CLK_USDHC2_ROOT>;
1284 clock-names = "ipg", "ahb", "per";
1285 fsl,tuning-start-tap = <20>;
1286 fsl,tuning-step = <2>;
1287 bus-width = <4>;
1288 status = "disabled";
1289 };
1290
1291 qspi0: spi@30bb0000 {
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1294 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1295 reg = <0x30bb0000 0x10000>,
1296 <0x08000000 0x10000000>;
1297 reg-names = "QuadSPI", "QuadSPI-memory";
1298 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1299 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
1300 <&clk IMX8MQ_CLK_QSPI_ROOT>;
1301 clock-names = "qspi_en", "qspi";
1302 status = "disabled";
1303 };
1304
1305 sdma1: sdma@30bd0000 {
1306 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1307 reg = <0x30bd0000 0x10000>;
1308 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1309 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
1310 <&clk IMX8MQ_CLK_AHB>;
1311 clock-names = "ipg", "ahb";
1312 #dma-cells = <3>;
1313 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1314 };
1315
1316 fec1: ethernet@30be0000 {
1317 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1318 reg = <0x30be0000 0x10000>;
1319 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1320 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1323 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1324 <&clk IMX8MQ_CLK_ENET1_ROOT>,
1325 <&clk IMX8MQ_CLK_ENET_TIMER>,
1326 <&clk IMX8MQ_CLK_ENET_REF>,
1327 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1328 clock-names = "ipg", "ahb", "ptp",
1329 "enet_clk_ref", "enet_out";
1330 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1331 <&clk IMX8MQ_CLK_ENET_TIMER>,
1332 <&clk IMX8MQ_CLK_ENET_REF>,
1333 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1334 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1335 <&clk IMX8MQ_SYS2_PLL_100M>,
1336 <&clk IMX8MQ_SYS2_PLL_125M>,
1337 <&clk IMX8MQ_SYS2_PLL_50M>;
1338 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1339 fsl,num-tx-queues = <3>;
1340 fsl,num-rx-queues = <3>;
1341 nvmem-cells = <&fec_mac_address>;
1342 nvmem-cell-names = "mac-address";
1343 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1344 status = "disabled";
1345 };
1346 };
1347
1348 noc: interconnect@32700000 {
1349 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1350 reg = <0x32700000 0x100000>;
1351 clocks = <&clk IMX8MQ_CLK_NOC>;
1352 fsl,ddrc = <&ddrc>;
1353 #interconnect-cells = <1>;
1354 operating-points-v2 = <&noc_opp_table>;
1355
1356 noc_opp_table: opp-table {
1357 compatible = "operating-points-v2";
1358
1359 opp-133M {
1360 opp-hz = /bits/ 64 <133333333>;
1361 };
1362
1363 opp-400M {
1364 opp-hz = /bits/ 64 <400000000>;
1365 };
1366
1367 opp-800M {
1368 opp-hz = /bits/ 64 <800000000>;
1369 };
1370 };
1371 };
1372
1373 aips4: bus@32c00000 { /* AIPS4 */
1374 compatible = "fsl,aips-bus", "simple-bus";
1375 reg = <0x32c00000 0x400000>;
1376 #address-cells = <1>;
1377 #size-cells = <1>;
1378 ranges = <0x32c00000 0x32c00000 0x400000>;
1379
1380 irqsteer: interrupt-controller@32e2d000 {
1381 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1382 reg = <0x32e2d000 0x1000>;
1383 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1384 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1385 clock-names = "ipg";
1386 fsl,channel = <0>;
1387 fsl,num-irqs = <64>;
1388 interrupt-controller;
1389 #interrupt-cells = <1>;
1390 };
1391 };
1392
1393 gpu: gpu@38000000 {
1394 compatible = "vivante,gc";
1395 reg = <0x38000000 0x40000>;
1396 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1398 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1399 <&clk IMX8MQ_CLK_GPU_AXI>,
1400 <&clk IMX8MQ_CLK_GPU_AHB>;
1401 clock-names = "core", "shader", "bus", "reg";
1402 #cooling-cells = <2>;
1403 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1404 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1405 <&clk IMX8MQ_CLK_GPU_AXI>,
1406 <&clk IMX8MQ_CLK_GPU_AHB>,
1407 <&clk IMX8MQ_GPU_PLL_BYPASS>;
1408 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1409 <&clk IMX8MQ_GPU_PLL_OUT>,
1410 <&clk IMX8MQ_GPU_PLL_OUT>,
1411 <&clk IMX8MQ_GPU_PLL_OUT>,
1412 <&clk IMX8MQ_GPU_PLL>;
1413 assigned-clock-rates = <800000000>, <800000000>,
1414 <800000000>, <800000000>, <0>;
1415 power-domains = <&pgc_gpu>;
1416 };
1417
1418 usb_dwc3_0: usb@38100000 {
1419 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1420 reg = <0x38100000 0x10000>;
1421 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
1422 <&clk IMX8MQ_CLK_USB_CORE_REF>,
1423 <&clk IMX8MQ_CLK_32K>;
1424 clock-names = "bus_early", "ref", "suspend";
1425 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1426 <&clk IMX8MQ_CLK_USB_CORE_REF>;
1427 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1428 <&clk IMX8MQ_SYS1_PLL_100M>;
1429 assigned-clock-rates = <500000000>, <100000000>;
1430 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1431 phys = <&usb3_phy0>, <&usb3_phy0>;
1432 phy-names = "usb2-phy", "usb3-phy";
1433 power-domains = <&pgc_otg1>;
1434 usb3-resume-missing-cas;
1435 status = "disabled";
1436 };
1437
1438 usb3_phy0: usb-phy@381f0040 {
1439 compatible = "fsl,imx8mq-usb-phy";
1440 reg = <0x381f0040 0x40>;
1441 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1442 clock-names = "phy";
1443 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1444 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1445 assigned-clock-rates = <100000000>;
1446 #phy-cells = <0>;
1447 status = "disabled";
1448 };
1449
1450 usb_dwc3_1: usb@38200000 {
1451 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1452 reg = <0x38200000 0x10000>;
1453 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1454 <&clk IMX8MQ_CLK_USB_CORE_REF>,
1455 <&clk IMX8MQ_CLK_32K>;
1456 clock-names = "bus_early", "ref", "suspend";
1457 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1458 <&clk IMX8MQ_CLK_USB_CORE_REF>;
1459 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1460 <&clk IMX8MQ_SYS1_PLL_100M>;
1461 assigned-clock-rates = <500000000>, <100000000>;
1462 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1463 phys = <&usb3_phy1>, <&usb3_phy1>;
1464 phy-names = "usb2-phy", "usb3-phy";
1465 power-domains = <&pgc_otg2>;
1466 usb3-resume-missing-cas;
1467 status = "disabled";
1468 };
1469
1470 usb3_phy1: usb-phy@382f0040 {
1471 compatible = "fsl,imx8mq-usb-phy";
1472 reg = <0x382f0040 0x40>;
1473 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1474 clock-names = "phy";
1475 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1476 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1477 assigned-clock-rates = <100000000>;
1478 #phy-cells = <0>;
1479 status = "disabled";
1480 };
1481
1482 vpu_g1: video-codec@38300000 {
1483 compatible = "nxp,imx8mq-vpu-g1";
1484 reg = <0x38300000 0x10000>;
1485 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1486 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
1487 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
1488 };
1489
1490 vpu_g2: video-codec@38310000 {
1491 compatible = "nxp,imx8mq-vpu-g2";
1492 reg = <0x38310000 0x10000>;
1493 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1494 clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
1495 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
1496 };
1497
1498 vpu_blk_ctrl: blk-ctrl@38320000 {
1499 compatible = "fsl,imx8mq-vpu-blk-ctrl";
1500 reg = <0x38320000 0x100>;
1501 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
1502 power-domain-names = "bus", "g1", "g2";
1503 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
1504 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
1505 clock-names = "g1", "g2";
1506 #power-domain-cells = <1>;
1507 };
1508
1509 pcie0: pcie@33800000 {
1510 compatible = "fsl,imx8mq-pcie";
1511 reg = <0x33800000 0x400000>,
1512 <0x1ff00000 0x80000>;
1513 reg-names = "dbi", "config";
1514 #address-cells = <3>;
1515 #size-cells = <2>;
1516 device_type = "pci";
1517 bus-range = <0x00 0xff>;
1518 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1519 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1520 num-lanes = <1>;
1521 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1522 interrupt-names = "msi";
1523 #interrupt-cells = <1>;
1524 interrupt-map-mask = <0 0 0 0x7>;
1525 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1526 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1527 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1528 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1529 fsl,max-link-speed = <2>;
1530 linux,pci-domain = <0>;
1531 power-domains = <&pgc_pcie>;
1532 resets = <&src IMX8MQ_RESET_PCIEPHY>,
1533 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1534 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1535 reset-names = "pciephy", "apps", "turnoff";
1536 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1537 <&clk IMX8MQ_CLK_PCIE1_PHY>,
1538 <&clk IMX8MQ_CLK_PCIE1_AUX>;
1539 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1540 <&clk IMX8MQ_SYS2_PLL_100M>,
1541 <&clk IMX8MQ_SYS1_PLL_80M>;
1542 assigned-clock-rates = <250000000>, <100000000>,
1543 <10000000>;
1544 status = "disabled";
1545 };
1546
1547 pcie1: pcie@33c00000 {
1548 compatible = "fsl,imx8mq-pcie";
1549 reg = <0x33c00000 0x400000>,
1550 <0x27f00000 0x80000>;
1551 reg-names = "dbi", "config";
1552 #address-cells = <3>;
1553 #size-cells = <2>;
1554 device_type = "pci";
1555 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
1556 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1557 num-lanes = <1>;
1558 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1559 interrupt-names = "msi";
1560 #interrupt-cells = <1>;
1561 interrupt-map-mask = <0 0 0 0x7>;
1562 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1563 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1564 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1565 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1566 fsl,max-link-speed = <2>;
1567 linux,pci-domain = <1>;
1568 power-domains = <&pgc_pcie>;
1569 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1570 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1571 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1572 reset-names = "pciephy", "apps", "turnoff";
1573 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1574 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1575 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1576 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1577 <&clk IMX8MQ_SYS2_PLL_100M>,
1578 <&clk IMX8MQ_SYS1_PLL_80M>;
1579 assigned-clock-rates = <250000000>, <100000000>,
1580 <10000000>;
1581 status = "disabled";
1582 };
1583
1584 gic: interrupt-controller@38800000 {
1585 compatible = "arm,gic-v3";
1586 reg = <0x38800000 0x10000>, /* GIC Dist */
1587 <0x38880000 0xc0000>, /* GICR */
1588 <0x31000000 0x2000>, /* GICC */
1589 <0x31010000 0x2000>, /* GICV */
1590 <0x31020000 0x2000>; /* GICH */
1591 #interrupt-cells = <3>;
1592 interrupt-controller;
1593 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1594 interrupt-parent = <&gic>;
1595 };
1596
1597 ddrc: memory-controller@3d400000 {
1598 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1599 reg = <0x3d400000 0x400000>;
1600 clock-names = "core", "pll", "alt", "apb";
1601 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1602 <&clk IMX8MQ_DRAM_PLL_OUT>,
1603 <&clk IMX8MQ_CLK_DRAM_ALT>,
1604 <&clk IMX8MQ_CLK_DRAM_APB>;
1605 status = "disabled";
1606 };
1607
1608 ddr-pmu@3d800000 {
1609 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1610 reg = <0x3d800000 0x400000>;
1611 interrupt-parent = <&gic>;
1612 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1613 };
1614 };
1615 };
