0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
0002 /*
0003 * Copyright 2019-2021 TQ-Systems GmbH
0004 */
0005
0006 #include "imx8mq.dtsi"
0007
0008 / {
0009 model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ";
0010 compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq";
0011
0012 memory@40000000 {
0013 device_type = "memory";
0014 /* our minimum RAM config will be 1024 MiB */
0015 reg = <0x00000000 0x40000000 0 0x40000000>;
0016 };
0017
0018 /* e-MMC IO, needed for HS modes */
0019 reg_vcc1v8: regulator-vcc1v8 {
0020 compatible = "regulator-fixed";
0021 regulator-name = "TQMA8MX_VCC1V8";
0022 regulator-min-microvolt = <1800000>;
0023 regulator-max-microvolt = <1800000>;
0024 };
0025
0026 reg_vcc3v3: regulator-vcc3v3 {
0027 compatible = "regulator-fixed";
0028 regulator-name = "TQMA8MX_VCC3V3";
0029 regulator-min-microvolt = <3300000>;
0030 regulator-max-microvolt = <3300000>;
0031 };
0032
0033 reg_vdd_arm: regulator-vdd-arm {
0034 compatible = "regulator-gpio";
0035 pinctrl-names = "default";
0036 pinctrl-0 = <&pinctrl_dvfs>;
0037 regulator-min-microvolt = <900000>;
0038 regulator-max-microvolt = <1000000>;
0039 regulator-name = "TQMa8Mx_DVFS";
0040 regulator-type = "voltage";
0041 regulator-settling-time-us = <150000>;
0042 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
0043 states = <900000 0x1 1000000 0x0>;
0044 };
0045
0046 reserved-memory {
0047 #address-cells = <2>;
0048 #size-cells = <2>;
0049 ranges;
0050
0051 /* global autoconfigured region for contiguous allocations */
0052 linux,cma {
0053 compatible = "shared-dma-pool";
0054 reusable;
0055 /* 640 MiB */
0056 size = <0 0x28000000>;
0057 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
0058 alloc-ranges = <0 0x40000000 0 0x78000000>;
0059 linux,cma-default;
0060 };
0061 };
0062 };
0063
0064 &A53_0 {
0065 cpu-supply = <®_vdd_arm>;
0066 };
0067
0068 &A53_1 {
0069 cpu-supply = <®_vdd_arm>;
0070 };
0071
0072 &A53_2 {
0073 cpu-supply = <®_vdd_arm>;
0074 };
0075
0076 &A53_3 {
0077 cpu-supply = <®_vdd_arm>;
0078 };
0079
0080 &gpu {
0081 status = "okay";
0082 };
0083
0084 &pgc_gpu {
0085 power-supply = <&sw1a_reg>;
0086 };
0087
0088 &pgc_vpu {
0089 power-supply = <&sw1c_reg>;
0090 };
0091
0092 &i2c1 {
0093 clock-frequency = <100000>;
0094 pinctrl-names = "default", "gpio";
0095 pinctrl-0 = <&pinctrl_i2c1>;
0096 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0097 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0098 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0099 status = "okay";
0100
0101 pfuze100: pmic@8 {
0102 compatible = "fsl,pfuze100";
0103 fsl,pfuze-support-disable-sw;
0104 reg = <0x8>;
0105
0106 regulators {
0107 /* VDD_GPU */
0108 sw1a_reg: sw1ab {
0109 regulator-min-microvolt = <825000>;
0110 regulator-max-microvolt = <1100000>;
0111 };
0112
0113 /* VDD_VPU */
0114 sw1c_reg: sw1c {
0115 regulator-min-microvolt = <825000>;
0116 regulator-max-microvolt = <1100000>;
0117 };
0118
0119 /* NVCC_DRAM */
0120 sw2_reg: sw2 {
0121 regulator-min-microvolt = <1100000>;
0122 regulator-max-microvolt = <1100000>;
0123 regulator-always-on;
0124 };
0125
0126 /* VDD_DRAM */
0127 sw3a_reg: sw3ab {
0128 regulator-min-microvolt = <825000>;
0129 regulator-max-microvolt = <1100000>;
0130 regulator-always-on;
0131 };
0132
0133 /* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */
0134 nvcc_1v8_reg: sw4 {
0135 regulator-min-microvolt = <1800000>;
0136 regulator-max-microvolt = <1800000>;
0137 regulator-always-on;
0138 };
0139
0140 swbst_reg: swbst {
0141 regulator-min-microvolt = <5000000>;
0142 regulator-max-microvolt = <5150000>;
0143 };
0144
0145 snvs_reg: vsnvs {
0146 regulator-min-microvolt = <1000000>;
0147 regulator-max-microvolt = <3000000>;
0148 regulator-always-on;
0149 };
0150
0151 vref_reg: vrefddr {
0152 regulator-always-on;
0153 };
0154
0155 /* not used */
0156 vgen1_reg: vgen1 {
0157 regulator-min-microvolt = <800000>;
0158 regulator-max-microvolt = <1550000>;
0159 };
0160
0161 /* VDD_PHY_0V9 */
0162 vgen2_reg: vgen2 {
0163 regulator-min-microvolt = <850000>;
0164 regulator-max-microvolt = <975000>;
0165 regulator-always-on;
0166 };
0167
0168 /* VDD_PHY_1V8 */
0169 vgen3_reg: vgen3 {
0170 regulator-min-microvolt = <1675000>;
0171 regulator-max-microvolt = <1975000>;
0172 regulator-always-on;
0173 };
0174
0175 /* VDDA_1V8 */
0176 vgen4_reg: vgen4 {
0177 regulator-min-microvolt = <1625000>;
0178 regulator-max-microvolt = <1875000>;
0179 regulator-always-on;
0180 };
0181
0182 /* VDD_PHY_3V3 */
0183 vgen5_reg: vgen5 {
0184 regulator-min-microvolt = <3075000>;
0185 regulator-max-microvolt = <3625000>;
0186 regulator-always-on;
0187 };
0188
0189 /* not used */
0190 vgen6_reg: vgen6 {
0191 regulator-min-microvolt = <1800000>;
0192 regulator-max-microvolt = <3300000>;
0193 };
0194 };
0195 };
0196
0197 sensor0: temperature-sensor-eeprom@1b {
0198 compatible = "nxp,se97", "jedec,jc-42.4-temp";
0199 reg = <0x1b>;
0200 };
0201
0202 pcf85063: rtc@51 {
0203 compatible = "nxp,pcf85063a";
0204 reg = <0x51>;
0205 pinctrl-names = "default";
0206 pinctrl-0 = <&pinctrl_rtc>;
0207 interrupt-parent = <&gpio1>;
0208 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
0209 quartz-load-femtofarads = <7000>;
0210
0211 clock {
0212 compatible = "fixed-clock";
0213 #clock-cells = <0>;
0214 clock-frequency = <32768>;
0215 };
0216 };
0217
0218 eeprom1: eeprom@53 {
0219 compatible = "nxp,se97b", "atmel,24c02";
0220 reg = <0x53>;
0221 pagesize = <16>;
0222 read-only;
0223 };
0224
0225 eeprom0: eeprom@57 {
0226 compatible = "atmel,24c64";
0227 reg = <0x57>;
0228 pagesize = <32>;
0229 };
0230 };
0231
0232 &pcie0 {
0233 /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
0234 vph-supply = <&vgen5_reg>;
0235 };
0236
0237 &pcie1 {
0238 /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
0239 vph-supply = <&vgen5_reg>;
0240 };
0241
0242 &qspi0 {
0243 pinctrl-names = "default";
0244 pinctrl-0 = <&pinctrl_qspi>;
0245 assigned-clocks = <&clk IMX8MQ_CLK_QSPI>;
0246 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>;
0247 status = "okay";
0248
0249 flash0: flash@0 {
0250 compatible = "jedec,spi-nor";
0251 reg = <0>;
0252 #address-cells = <1>;
0253 #size-cells = <1>;
0254 spi-max-frequency = <84000000>;
0255 spi-tx-bus-width = <1>;
0256 spi-rx-bus-width = <4>;
0257 };
0258 };
0259
0260 &usdhc1 {
0261 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0262 pinctrl-0 = <&pinctrl_usdhc1>;
0263 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0264 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0265 bus-width = <8>;
0266 non-removable;
0267 no-sd;
0268 no-sdio;
0269 vmmc-supply = <®_vcc3v3>;
0270 vqmmc-supply = <®_vcc1v8>;
0271 status = "okay";
0272 };
0273
0274 /* Attention: wdog reset forcing POR needs baseboard support */
0275 &wdog1 {
0276 status = "okay";
0277 };
0278
0279 &iomuxc {
0280 pinctrl_dvfs: dvfsgrp {
0281 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16>;
0282 };
0283
0284 pinctrl_i2c1: i2c1grp {
0285 fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f>,
0286 <MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f>;
0287 };
0288
0289 pinctrl_i2c1_gpio: i2c1gpiogrp {
0290 fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000074>,
0291 <MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000074>;
0292 };
0293
0294 pinctrl_qspi: qspigrp {
0295 fsl,pins = <MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x97>,
0296 <MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
0297 <MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x97>,
0298 <MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x97>,
0299 <MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x97>,
0300 <MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x97>;
0301 };
0302
0303 pinctrl_rtc: rtcgrp {
0304 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41>;
0305 };
0306
0307 pinctrl_usdhc1: usdhc1grp {
0308 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83>,
0309 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3>,
0310 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3>,
0311 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3>,
0312 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3>,
0313 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3>,
0314 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3>,
0315 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3>,
0316 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3>,
0317 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3>,
0318 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83>,
0319 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
0320 };
0321
0322 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0323 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85>,
0324 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5>,
0325 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5>,
0326 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5>,
0327 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5>,
0328 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5>,
0329 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5>,
0330 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5>,
0331 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5>,
0332 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5>,
0333 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85>,
0334 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
0335 };
0336
0337 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0338 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87>,
0339 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7>,
0340 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7>,
0341 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7>,
0342 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7>,
0343 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7>,
0344 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7>,
0345 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7>,
0346 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7>,
0347 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7>,
0348 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87>,
0349 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
0350 };
0351
0352 pinctrl_wdog: wdoggrp {
0353 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>;
0354 };
0355 };
