0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
0002 /*
0003 * Copyright 2019-2021 TQ-Systems GmbH
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx8mq-tqma8mq.dtsi"
0009 #include "mba8mx.dtsi"
0010
0011 / {
0012 model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
0013 compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
0014
0015 aliases {
0016 eeprom0 = &eeprom3;
0017 mmc0 = &usdhc1;
0018 mmc1 = &usdhc2;
0019 rtc0 = &pcf85063;
0020 rtc1 = &snvs_rtc;
0021 };
0022
0023 extcon_usbotg: extcon-usbotg0 {
0024 compatible = "linux,extcon-usb-gpio";
0025 pinctrl-names = "default";
0026 pinctrl-0 = <&pinctrl_usbcon0>;
0027 id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
0028 };
0029
0030 pcie0_refclk: pcie0-refclk {
0031 compatible = "fixed-clock";
0032 #clock-cells = <0>;
0033 clock-frequency = <100000000>;
0034 };
0035
0036 pcie1_refclk: pcie1-refclk {
0037 compatible = "fixed-clock";
0038 #clock-cells = <0>;
0039 clock-frequency = <100000000>;
0040 };
0041
0042 reg_otg_vbus: regulator-otg-vbus {
0043 compatible = "regulator-fixed";
0044 pinctrl-names = "default";
0045 pinctrl-0 = <&pinctrl_regotgvbus>;
0046 regulator-name = "MBA8MQ_OTG_VBUS";
0047 regulator-min-microvolt = <5000000>;
0048 regulator-max-microvolt = <5000000>;
0049 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0050 enable-active-high;
0051 };
0052
0053 reg_usdhc2_vmmc: regulator-vmmc {
0054 compatible = "regulator-fixed";
0055 regulator-name = "VSD_3V3";
0056 regulator-min-microvolt = <3300000>;
0057 regulator-max-microvolt = <3300000>;
0058 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0059 enable-active-high;
0060 };
0061 };
0062
0063 &btn2 {
0064 gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
0065 };
0066
0067 &gpio_leds {
0068 led3 {
0069 label = "led3";
0070 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
0071 };
0072 };
0073
0074 &i2c1 {
0075 expander2: gpio@25 {
0076 compatible = "nxp,pca9555";
0077 reg = <0x25>;
0078 gpio-controller;
0079 #gpio-cells = <2>;
0080 vcc-supply = <®_vcc_3v3>;
0081 pinctrl-names = "default";
0082 pinctrl-0 = <&pinctrl_expander>;
0083 interrupt-parent = <&gpio1>;
0084 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
0085 interrupt-controller;
0086 #interrupt-cells = <2>;
0087
0088 mpcie-rst-hog {
0089 gpio-hog;
0090 gpios = <13 0>;
0091 output-high;
0092 line-name = "MPCIE_RST#";
0093 };
0094 };
0095 };
0096
0097 &irqsteer {
0098 status = "okay";
0099 };
0100
0101 &led2 {
0102 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
0103 };
0104
0105 &pcie0 {
0106 reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
0107 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
0108 <&clk IMX8MQ_CLK_PCIE1_AUX>,
0109 <&clk IMX8MQ_CLK_PCIE1_PHY>,
0110 <&pcie0_refclk>;
0111 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
0112 epdev_on-supply = <®_vcc_3v3>;
0113 hard-wired = <1>;
0114 status = "okay";
0115 };
0116
0117 /*
0118 * miniPCIe, also usable for cards with USB. Therefore configure the reset as
0119 * static gpio hog.
0120 */
0121 &pcie1 {
0122 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
0123 <&clk IMX8MQ_CLK_PCIE2_AUX>,
0124 <&clk IMX8MQ_CLK_PCIE2_PHY>,
0125 <&pcie1_refclk>;
0126 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
0127 epdev_on-supply = <®_vcc_3v3>;
0128 hard-wired = <1>;
0129 status = "okay";
0130 };
0131
0132 &sai3 {
0133 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
0134 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
0135 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
0136 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
0137 <&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
0138 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
0139 <&clk IMX8MQ_AUDIO_PLL2_OUT>;
0140 };
0141
0142 &tlv320aic3x04 {
0143 clock-names = "mclk";
0144 clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>;
0145 };
0146
0147 &uart1 {
0148 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
0149 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
0150 };
0151
0152 &uart2 {
0153 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
0154 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
0155 };
0156
0157 /* console */
0158 &uart3 {
0159 assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
0160 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
0161 };
0162
0163 &usb3_phy0 {
0164 vbus-supply = <®_otg_vbus>;
0165 status = "okay";
0166 };
0167
0168 &usb_dwc3_0 {
0169 /* we implement dual role but not full featured OTG */
0170 extcon = <&extcon_usbotg>;
0171 hnp-disable;
0172 srp-disable;
0173 adp-disable;
0174 /* OC not supported due to non matching active polarity */
0175 disable-over-current;
0176 dr_mode = "otg";
0177 status = "okay";
0178 };
0179
0180 &usb3_phy1 {
0181 status = "okay";
0182 };
0183
0184 &usb_dwc3_1 {
0185 status = "okay";
0186 dr_mode = "host";
0187 };
0188
0189 &wdog1 {
0190 pinctrl-names = "default";
0191 pinctrl-0 = <&pinctrl_wdog>;
0192 fsl,ext-reset-output;
0193 status = "okay";
0194 };
0195
0196 &iomuxc {
0197 pinctrl_ecspi1: ecspi1grp {
0198 fsl,pins = <MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x0000004e>,
0199 <MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x0000004e>,
0200 <MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x0000004e>,
0201 <MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0000004e>;
0202 };
0203
0204 pinctrl_ecspi2: ecspi2grp {
0205 fsl,pins = <MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x0000004e>,
0206 <MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x0000004e>,
0207 <MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x0000004e>,
0208 <MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x0000004e>;
0209 };
0210
0211 pinctrl_expander: expandergrp {
0212 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0xd6>;
0213 };
0214
0215 pinctrl_fec1: fec1grp {
0216 fsl,pins = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
0217 <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23>,
0218 <MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
0219 <MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
0220 <MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
0221 <MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
0222 <MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
0223 <MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
0224 <MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
0225 <MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
0226 <MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
0227 <MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
0228 <MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
0229 <MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>;
0230 };
0231
0232 pinctrl_gpiobutton: gpiobuttongrp {
0233 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41>,
0234 <MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41>,
0235 <MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41>;
0236 };
0237
0238 pinctrl_gpioled: gpioledgrp {
0239 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x41>,
0240 <MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41>,
0241 <MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41>;
0242 };
0243
0244 pinctrl_i2c2: i2c2grp {
0245 fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067>,
0246 <MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067>;
0247 };
0248
0249 pinctrl_i2c2_gpio: i2c2gpiogrp {
0250 fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x40000067>,
0251 <MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x40000067>;
0252 };
0253
0254 pinctrl_i2c3: i2c3grp {
0255 fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000067>,
0256 <MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000067>;
0257 };
0258
0259 pinctrl_i2c3_gpio: i2c3gpiogrp {
0260 fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x40000067>,
0261 <MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x40000067>;
0262 };
0263
0264 pinctrl_pwm3: pwm3grp {
0265 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x16>;
0266 };
0267
0268 pinctrl_pwm4: pwm4grp {
0269 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x16>;
0270 };
0271
0272 pinctrl_regotgvbus: reggotgvbusgrp {
0273 /* USB1 OTG PWR as GPIO */
0274 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x06>;
0275 };
0276
0277 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0278 fsl,pins = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1>;
0279 };
0280
0281 pinctrl_sai3: sai3grp {
0282 fsl,pins = <MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6>,
0283 <MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6>,
0284 <MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6>,
0285 <MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6>,
0286 <MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6>,
0287 <MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6>,
0288 <MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6>;
0289 };
0290
0291 pinctrl_uart1: uart1grp {
0292 fsl,pins = <MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79>,
0293 <MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79>;
0294 };
0295
0296 pinctrl_uart2: uart2grp {
0297 fsl,pins = <MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79>,
0298 <MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79>;
0299 };
0300
0301 pinctrl_uart3: uart3grp {
0302 fsl,pins = <MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79>,
0303 <MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79>;
0304 };
0305
0306 pinctrl_uart4: uart4grp {
0307 fsl,pins = <MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79>,
0308 <MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79>;
0309 };
0310
0311 pinctrl_usbcon0: usb0congrp {
0312 /* ID: floating / high: device, low: host -> use PU */
0313 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xe6>;
0314 };
0315
0316 pinctrl_usdhc2: usdhc2grp {
0317 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83>,
0318 <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3>,
0319 <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3>,
0320 <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3>,
0321 <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3>,
0322 <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3>,
0323 <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>;
0324 };
0325
0326 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0327 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85>,
0328 <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5>,
0329 <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5>,
0330 <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5>,
0331 <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5>,
0332 <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5>,
0333 <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>;
0334 };
0335
0336 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0337 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f>,
0338 <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7>,
0339 <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7>,
0340 <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7>,
0341 <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7>,
0342 <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7>,
0343 <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1>;
0344 };
0345
0346 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
0347 fsl,pins = <MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41>;
0348 };
0349 };
