0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2019 Einfochips
0004 * Copyright 2019 Linaro Ltd.
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "imx8mq.dtsi"
0010
0011 / {
0012 model = "Einfochips i.MX8MQ Thor96";
0013 compatible = "einfochips,imx8mq-thor96", "fsl,imx8mq";
0014
0015 chosen {
0016 stdout-path = &uart1;
0017 };
0018
0019 memory@40000000 {
0020 device_type = "memory";
0021 reg = <0x00000000 0x40000000 0 0x80000000>;
0022 };
0023
0024 leds {
0025 compatible = "gpio-leds";
0026 pinctrl-names = "default";
0027 pinctrl-0 = <&pinctrl_leds>;
0028
0029 user-led1 {
0030 label = "green:user1";
0031 gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
0032 linux,default-trigger = "heartbeat";
0033 };
0034
0035 user-led2 {
0036 label = "green:user2";
0037 gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
0038 linux,default-trigger = "none";
0039 };
0040
0041 user-led3 {
0042 label = "green:user3";
0043 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
0044 linux,default-trigger = "mmc1";
0045 default-state = "off";
0046 };
0047
0048 user-led4 {
0049 label = "green:user4";
0050 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
0051 panic-indicator;
0052 linux,default-trigger = "none";
0053 };
0054
0055 wlan-active-led {
0056 label = "yellow:wlan";
0057 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
0058 linux,default-trigger = "phy0tx";
0059 default-state = "off";
0060 };
0061
0062 bt-active-led {
0063 label = "blue:bt";
0064 gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
0065 linux,default-trigger = "hci0-power";
0066 default-state = "off";
0067 };
0068 };
0069
0070 reg_usdhc1_vmmc: reg-usdhc1-vmmc {
0071 compatible = "regulator-fixed";
0072 regulator-name = "VDD_3V3";
0073 regulator-min-microvolt = <3300000>;
0074 regulator-max-microvolt = <3300000>;
0075 regulator-always-on;
0076 };
0077
0078 reg_usdhc1_vqmmc: reg-usdhc1-vqmmc {
0079 compatible = "regulator-fixed";
0080 regulator-name = "VCC_1V8_EXT";
0081 regulator-min-microvolt = <1800000>;
0082 regulator-max-microvolt = <1800000>;
0083 regulator-always-on;
0084 };
0085
0086 reg_usdhc2_vmmc: reg-usdhc2-vmmc {
0087 compatible = "regulator-fixed";
0088 regulator-name = "VSD_3V3";
0089 regulator-min-microvolt = <3300000>;
0090 regulator-max-microvolt = <3300000>;
0091 regulator-always-on;
0092 pinctrl-names = "default";
0093 pinctrl-0 = <&pinctrl_reg_usdhc2>;
0094 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0095 enable-active-high;
0096 };
0097
0098 reg_usdhc2_vqmmc: reg-usdhc2-vqmmc {
0099 compatible = "regulator-fixed";
0100 regulator-name = "NVCC_SD2";
0101 regulator-min-microvolt = <3300000>;
0102 regulator-max-microvolt = <3300000>;
0103 regulator-always-on;
0104 };
0105
0106 sdio_pwrseq: sdio-pwrseq {
0107 compatible = "mmc-pwrseq-simple";
0108 pinctrl-names = "default";
0109 pinctrl-0 = <&pinctrl_wifi_reg_on>;
0110 gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
0111 };
0112 };
0113
0114 /* LS-SPI0 */
0115 &ecspi2 {
0116 pinctrl-names = "default";
0117 pinctrl-0 = <&pinctrl_ecspi2>;
0118 status = "okay";
0119 };
0120
0121 &fec1 {
0122 pinctrl-names = "default";
0123 pinctrl-0 = <&pinctrl_fec1>;
0124 phy-mode = "rgmii-id";
0125 phy-handle = <ðphy>;
0126 fsl,magic-packet;
0127 status = "okay";
0128
0129 mdio {
0130 #address-cells = <1>;
0131 #size-cells = <0>;
0132
0133 ethphy: ethernet-phy@3 {
0134 compatible = "ethernet-phy-ieee802.3-c22";
0135 reg = <3>;
0136 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
0137 };
0138 };
0139 };
0140
0141 /* LS-I2C0 */
0142 &i2c1 {
0143 clock-frequency = <100000>;
0144 pinctrl-names = "default";
0145 pinctrl-0 = <&pinctrl_i2c1>;
0146 status = "okay";
0147
0148 pmic@8 {
0149 compatible = "fsl,pfuze100";
0150 reg = <0x8>;
0151
0152 regulators {
0153 sw1a_reg: sw1ab {
0154 regulator-min-microvolt = <300000>;
0155 regulator-max-microvolt = <1875000>;
0156 };
0157
0158 sw1c_reg: sw1c {
0159 regulator-min-microvolt = <300000>;
0160 regulator-max-microvolt = <1875000>;
0161 };
0162
0163 sw2_reg: sw2 {
0164 regulator-min-microvolt = <800000>;
0165 regulator-max-microvolt = <3300000>;
0166 regulator-always-on;
0167 };
0168
0169 sw3a_reg: sw3ab {
0170 regulator-min-microvolt = <400000>;
0171 regulator-max-microvolt = <1975000>;
0172 regulator-always-on;
0173 };
0174
0175 sw4_reg: sw4 {
0176 regulator-min-microvolt = <800000>;
0177 regulator-max-microvolt = <3300000>;
0178 regulator-always-on;
0179 };
0180
0181 swbst_reg: swbst {
0182 regulator-min-microvolt = <5000000>;
0183 regulator-max-microvolt = <5150000>;
0184 };
0185
0186 snvs_reg: vsnvs {
0187 regulator-min-microvolt = <1000000>;
0188 regulator-max-microvolt = <3000000>;
0189 regulator-always-on;
0190 };
0191
0192 vref_reg: vrefddr {
0193 regulator-always-on;
0194 };
0195
0196 vgen1_reg: vgen1 {
0197 regulator-min-microvolt = <800000>;
0198 regulator-max-microvolt = <1550000>;
0199 };
0200
0201 vgen2_reg: vgen2 {
0202 regulator-min-microvolt = <800000>;
0203 regulator-max-microvolt = <1550000>;
0204 regulator-always-on;
0205 };
0206
0207 vgen3_reg: vgen3 {
0208 regulator-min-microvolt = <1800000>;
0209 regulator-max-microvolt = <3300000>;
0210 regulator-always-on;
0211 };
0212
0213 vgen4_reg: vgen4 {
0214 regulator-min-microvolt = <1800000>;
0215 regulator-max-microvolt = <3300000>;
0216 regulator-always-on;
0217 };
0218
0219 vgen5_reg: vgen5 {
0220 regulator-min-microvolt = <1800000>;
0221 regulator-max-microvolt = <3300000>;
0222 regulator-always-on;
0223 };
0224
0225 vgen6_reg: vgen6 {
0226 regulator-min-microvolt = <1800000>;
0227 regulator-max-microvolt = <3300000>;
0228 };
0229 };
0230 };
0231 };
0232
0233 /* LS-I2C1 */
0234 &i2c2 {
0235 clock-frequency = <100000>;
0236 pinctrl-names = "default";
0237 pinctrl-0 = <&pinctrl_i2c2>;
0238 status = "okay";
0239
0240 eeprom: eeprom@50 {
0241 compatible = "atmel,24c256";
0242 reg = <0x50>;
0243 };
0244 };
0245
0246 /* HS-I2C2 */
0247 &i2c3 {
0248 clock-frequency = <100000>;
0249 pinctrl-names = "default";
0250 pinctrl-0 = <&pinctrl_i2c3>;
0251 status = "okay";
0252 };
0253
0254 /* HS-I2C3 */
0255 &i2c4 {
0256 clock-frequency = <100000>;
0257 pinctrl-names = "default";
0258 pinctrl-0 = <&pinctrl_i2c4>;
0259 status = "okay";
0260 };
0261
0262 &pgc_gpu {
0263 power-supply = <&sw1a_reg>;
0264 };
0265
0266 &pgc_vpu {
0267 power-supply = <&sw1c_reg>;
0268 };
0269
0270 &qspi0 {
0271 pinctrl-names = "default";
0272 pinctrl-0 = <&pinctrl_qspi0>;
0273 status = "okay";
0274
0275 flash@0 {
0276 compatible = "jedec,spi-nor";
0277 spi-max-frequency = <100000000>;
0278 reg = <0>;
0279 };
0280 };
0281
0282 /* Debug UART */
0283 &uart1 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_uart1>;
0286 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
0287 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
0288 status = "okay";
0289 };
0290
0291 /* LS-UART0 */
0292 &uart2 {
0293 pinctrl-names = "default";
0294 pinctrl-0 = <&pinctrl_uart2>;
0295 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
0296 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
0297 uart-has-rtscts;
0298 status = "okay";
0299
0300 bluetooth {
0301 compatible = "brcm,bcm43438-bt";
0302 device-wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
0303 host-wakeup-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
0304 shutdown-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
0305 pinctrl-names = "default";
0306 pinctrl-0 = <&pinctrl_bt_gpios>;
0307 };
0308 };
0309
0310 /* LS-UART1 */
0311 &uart3 {
0312 pinctrl-names = "default";
0313 pinctrl-0 = <&pinctrl_uart3>;
0314 assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
0315 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
0316 status = "okay";
0317 };
0318
0319 &usb3_phy1 {
0320 status = "okay";
0321 };
0322
0323 &usb_dwc3_1 {
0324 dr_mode = "host";
0325 status = "okay";
0326 };
0327
0328 /* SDIO */
0329 &usdhc1 {
0330 #address-cells = <0x1>;
0331 #size-cells = <0x0>;
0332 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0333 pinctrl-0 = <&pinctrl_usdhc1>;
0334 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0335 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0336 vmmc-supply = <®_usdhc1_vmmc>;
0337 vqmmc-supply = <®_usdhc1_vqmmc>;
0338 mmc-pwrseq = <&sdio_pwrseq>;
0339 bus-width = <4>;
0340 non-removable;
0341 no-sd;
0342 no-emmc;
0343 status = "okay";
0344
0345 brcmf: wifi@1 {
0346 reg = <1>;
0347 compatible = "brcm,bcm4329-fmac";
0348 };
0349 };
0350
0351 /* uSD */
0352 &usdhc2 {
0353 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0354 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0355 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0356 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0357 vmmc-supply = <®_usdhc2_vmmc>;
0358 vqmmc-supply = <®_usdhc2_vqmmc>;
0359 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0360 bus-width = <4>;
0361 no-sdio;
0362 no-emmc;
0363 disable-wp;
0364 status = "okay";
0365 };
0366
0367 &wdog1 {
0368 pinctrl-names = "default";
0369 pinctrl-0 = <&pinctrl_wdog>;
0370 fsl,ext-reset-output;
0371 status = "okay";
0372 };
0373
0374 &iomuxc {
0375 pinctrl_bt_gpios: btgpiosgrp {
0376 fsl,pins = <
0377 MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
0378 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19
0379 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
0380 >;
0381 };
0382
0383 pinctrl_ecspi2: ecspi2grp {
0384 fsl,pins = <
0385 MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x16
0386 MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x16
0387 MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x16
0388 MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x16
0389 >;
0390 };
0391
0392 pinctrl_fec1: fec1grp {
0393 fsl,pins = <
0394 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x4
0395 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x24
0396 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1c
0397 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1c
0398 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1c
0399 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1c
0400 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0401 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0402 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0403 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0404 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1c
0405 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0406 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0407 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1c
0408 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
0409 >;
0410 };
0411
0412 pinctrl_i2c1: i2c1grp {
0413 fsl,pins = <
0414 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
0415 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
0416 >;
0417 };
0418
0419 pinctrl_i2c2: i2c2grp {
0420 fsl,pins = <
0421 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
0422 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
0423 >;
0424 };
0425
0426 pinctrl_i2c3: i2c3grp {
0427 fsl,pins = <
0428 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
0429 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
0430 >;
0431 };
0432
0433 pinctrl_i2c4: i2c4grp {
0434 fsl,pins = <
0435 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
0436 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
0437 >;
0438 };
0439
0440 pinctrl_leds: ledsgrp {
0441 fsl,pins = <
0442 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x19
0443 MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
0444 MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
0445 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
0446 MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19
0447 MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19
0448 >;
0449 };
0450
0451 pinctrl_qspi0: qspi0grp {
0452 fsl,pins = <
0453 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
0454 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0455 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0456 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0457 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0458 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0459
0460 >;
0461 };
0462
0463 pinctrl_reg_usdhc2: regusdhc2grp {
0464 fsl,pins = <
0465 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
0466 >;
0467 };
0468
0469 pinctrl_uart1: uart1grp {
0470 fsl,pins = <
0471 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
0472 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
0473 >;
0474 };
0475
0476 pinctrl_uart2: uart2grp {
0477 fsl,pins = <
0478 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
0479 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
0480 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
0481 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
0482 >;
0483 };
0484
0485 pinctrl_uart3: uart3grp {
0486 fsl,pins = <
0487 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
0488 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
0489 >;
0490 };
0491
0492 pinctrl_usdhc1: usdhc1grp {
0493 fsl,pins = <
0494 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
0495 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
0496 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
0497 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
0498 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
0499 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
0500 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85
0501 >;
0502 };
0503
0504 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0505 fsl,pins = <
0506 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
0507 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
0508 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
0509 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
0510 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
0511 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
0512 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85
0513 >;
0514 };
0515
0516 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0517 fsl,pins = <
0518 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
0519 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
0520 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
0521 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
0522 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
0523 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
0524 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85
0525 >;
0526 };
0527
0528 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0529 fsl,pins = <
0530 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
0531 >;
0532 };
0533
0534 pinctrl_usdhc2: usdhc2grp {
0535 fsl,pins = <
0536 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
0537 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
0538 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
0539 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
0540 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
0541 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
0542 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0543 >;
0544 };
0545
0546 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0547 fsl,pins = <
0548 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8c
0549 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcc
0550 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcc
0551 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcc
0552 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcc
0553 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcc
0554 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0555 >;
0556 };
0557
0558 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0559 fsl,pins = <
0560 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9c
0561 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdc
0562 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdc
0563 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdc
0564 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdc
0565 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdc
0566 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xcc
0567 >;
0568 };
0569
0570 pinctrl_wdog: wdoggrp {
0571 fsl,pins = <
0572 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0573 >;
0574 };
0575
0576 pinctrl_wifi_reg_on: wifiregongrp {
0577 fsl,pins = <
0578 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059
0579 >;
0580 };
0581 };
