0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
0004 */
0005
0006 #include "imx8mq.dtsi"
0007
0008 / {
0009 reg_vdd_3v3: regulator-vdd-3v3 {
0010 compatible = "regulator-fixed";
0011 regulator-always-on;
0012 regulator-name = "vdd_3v3";
0013 regulator-min-microvolt = <3300000>;
0014 regulator-max-microvolt = <3300000>;
0015 };
0016 };
0017
0018 &fec1 {
0019 pinctrl-names = "default";
0020 pinctrl-0 = <&pinctrl_fec1>;
0021 phy-mode = "rgmii-id";
0022 phy-handle = <ðphy0>;
0023 fsl,magic-packet;
0024 status = "okay";
0025
0026 mdio {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 ethphy0: ethernet-phy@4 {
0031 compatible = "ethernet-phy-ieee802.3-c22";
0032 reg = <4>;
0033 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
0034 reset-assert-us = <2000>;
0035 };
0036 };
0037 };
0038
0039 &i2c1 {
0040 pinctrl-names = "default";
0041 pinctrl-0 = <&pinctrl_i2c1>;
0042 clock-frequency = <400000>;
0043 status = "okay";
0044
0045 pmic: pmic@8 {
0046 compatible = "fsl,pfuze100";
0047 reg = <0x08>;
0048
0049 regulators {
0050 sw1a_reg: sw1ab {
0051 regulator-min-microvolt = <300000>;
0052 regulator-max-microvolt = <1875000>;
0053 };
0054
0055 sw1c_reg: sw1c {
0056 regulator-min-microvolt = <300000>;
0057 regulator-max-microvolt = <1875000>;
0058 };
0059
0060 sw2_reg: sw2 {
0061 regulator-min-microvolt = <800000>;
0062 regulator-max-microvolt = <3300000>;
0063 regulator-always-on;
0064 };
0065
0066 sw3a_reg: sw3ab {
0067 regulator-min-microvolt = <400000>;
0068 regulator-max-microvolt = <1975000>;
0069 regulator-always-on;
0070 };
0071
0072 sw4_reg: sw4 {
0073 regulator-min-microvolt = <800000>;
0074 regulator-max-microvolt = <3300000>;
0075 regulator-always-on;
0076 };
0077
0078 swbst_reg: swbst {
0079 regulator-min-microvolt = <5000000>;
0080 regulator-max-microvolt = <5150000>;
0081 };
0082
0083 snvs_reg: vsnvs {
0084 regulator-min-microvolt = <1000000>;
0085 regulator-max-microvolt = <3000000>;
0086 regulator-always-on;
0087 };
0088
0089 vref_reg: vrefddr {
0090 regulator-always-on;
0091 };
0092
0093 vgen1_reg: vgen1 {
0094 regulator-min-microvolt = <800000>;
0095 regulator-max-microvolt = <1550000>;
0096 };
0097
0098 vgen2_reg: vgen2 {
0099 regulator-min-microvolt = <800000>;
0100 regulator-max-microvolt = <1550000>;
0101 regulator-always-on;
0102 };
0103
0104 vgen3_reg: vgen3 {
0105 regulator-min-microvolt = <1800000>;
0106 regulator-max-microvolt = <3300000>;
0107 regulator-always-on;
0108 };
0109
0110 vgen4_reg: vgen4 {
0111 regulator-min-microvolt = <1800000>;
0112 regulator-max-microvolt = <3300000>;
0113 regulator-always-on;
0114 };
0115
0116 vgen5_reg: vgen5 {
0117 regulator-min-microvolt = <1800000>;
0118 regulator-max-microvolt = <3300000>;
0119 regulator-always-on;
0120 };
0121
0122 vgen6_reg: vgen6 {
0123 regulator-min-microvolt = <1800000>;
0124 regulator-max-microvolt = <3300000>;
0125 };
0126 };
0127 };
0128
0129 eeprom@50 {
0130 compatible = "atmel,24c01";
0131 reg = <0x50>;
0132 status = "okay";
0133 };
0134 };
0135
0136 &pgc_gpu{
0137 power-supply = <&sw1a_reg>;
0138 };
0139
0140 &pgc_vpu {
0141 power-supply = <&sw1c_reg>;
0142 };
0143
0144 &qspi0 {
0145 pinctrl-names = "default";
0146 pinctrl-0 = <&pinctrl_qspi>;
0147 status = "okay";
0148
0149 /* SPI flash; not assembled by default */
0150 spi_flash: flash@0 {
0151 #address-cells = <1>;
0152 #size-cells = <1>;
0153 reg = <0>;
0154 compatible = "micron,n25q256a", "jedec,spi-nor";
0155 spi-max-frequency = <29000000>;
0156 status = "disabled";
0157 };
0158 };
0159
0160 &uart1 { /* console */
0161 pinctrl-names = "default";
0162 pinctrl-0 = <&pinctrl_uart1>;
0163 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
0164 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
0165 assigned-clock-rates = <25000000>;
0166 status = "okay";
0167 };
0168
0169 &uart4 { /* ublox BT */
0170 pinctrl-names = "default";
0171 pinctrl-0 = <&pinctrl_uart4>;
0172 assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
0173 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
0174 assigned-clock-rates = <80000000>;
0175 status = "okay";
0176 };
0177
0178 &usdhc1 {
0179 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
0180 assigned-clock-rates = <400000000>;
0181 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0182 pinctrl-0 = <&pinctrl_usdhc1>;
0183 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0184 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0185 bus-width = <8>;
0186 non-removable;
0187 status = "okay";
0188 };
0189
0190 &wdog1 {
0191 pinctrl-names = "default";
0192 pinctrl-0 = <&pinctrl_wdog>;
0193 fsl,ext-reset-output;
0194 status = "okay";
0195 };
0196
0197 &iomuxc {
0198 pinctrl_fec1: fec1grp {
0199 fsl,pins = <
0200 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0201 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
0202 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0203 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0204 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0205 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0206 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0207 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0208 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0209 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0210 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0211 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0212 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0213 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0214 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
0215 >;
0216 };
0217
0218 pinctrl_i2c1: i2c1grp {
0219 fsl,pins = <
0220 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
0221 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
0222 >;
0223 };
0224
0225 pinctrl_pcie0: pcie0grp {
0226 fsl,pins = <
0227 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74
0228 MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16
0229 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
0230 >;
0231 };
0232
0233 pinctrl_qspi: qspigrp {
0234 fsl,pins = <
0235 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
0236 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0237 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0238 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0239 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0240 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0241
0242 >;
0243 };
0244
0245 pinctrl_uart1: uart1grp {
0246 fsl,pins = <
0247 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
0248 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
0249 MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
0250 >;
0251 };
0252
0253 pinctrl_uart4: uart4grp {
0254 fsl,pins = <
0255 MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
0256 MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
0257 MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19
0258 >;
0259 };
0260
0261 pinctrl_usdhc1: usdhc1grp {
0262 fsl,pins = <
0263 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
0264 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
0265 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
0266 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
0267 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
0268 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
0269 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
0270 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
0271 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
0272 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
0273 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
0274 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0275 >;
0276 };
0277
0278 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0279 fsl,pins = <
0280 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
0281 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
0282 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
0283 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
0284 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
0285 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
0286 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
0287 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
0288 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
0289 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
0290 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
0291 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0292 >;
0293 };
0294
0295 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0296 fsl,pins = <
0297 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
0298 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
0299 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
0300 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
0301 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
0302 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
0303 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
0304 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
0305 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
0306 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
0307 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
0308 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0309 >;
0310 };
0311
0312 pinctrl_wdog: wdoggrp {
0313 fsl,pins = <
0314 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0315 >;
0316 };
0317 };
