0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright 2017-2019 NXP
0004 */
0005
0006 /dts-v1/;
0007
0008 #include "imx8mq.dtsi"
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010
0011 / {
0012 model = "Google i.MX8MQ Phanbell";
0013 compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
0014
0015 chosen {
0016 stdout-path = &uart1;
0017 };
0018
0019 memory@40000000 {
0020 device_type = "memory";
0021 reg = <0x00000000 0x40000000 0 0x40000000>;
0022 };
0023
0024 pmic_osc: clock-pmic {
0025 compatible = "fixed-clock";
0026 #clock-cells = <0>;
0027 clock-frequency = <32768>;
0028 clock-output-names = "pmic_osc";
0029 };
0030
0031 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
0032 compatible = "regulator-fixed";
0033 regulator-name = "VSD_3V3";
0034 regulator-min-microvolt = <3300000>;
0035 regulator-max-microvolt = <3300000>;
0036 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0037 enable-active-high;
0038 };
0039
0040 fan: gpio-fan {
0041 compatible = "gpio-fan";
0042 gpio-fan,speed-map = <0 0 8600 1>;
0043 gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
0044 #cooling-cells = <2>;
0045 pinctrl-names = "default";
0046 pinctrl-0 = <&pinctrl_gpio_fan>;
0047 status = "okay";
0048 };
0049 };
0050
0051 &A53_0 {
0052 cpu-supply = <&buck2>;
0053 };
0054
0055 &A53_1 {
0056 cpu-supply = <&buck2>;
0057 };
0058
0059 &A53_2 {
0060 cpu-supply = <&buck2>;
0061 };
0062
0063 &A53_3 {
0064 cpu-supply = <&buck2>;
0065 };
0066
0067 &cpu_thermal {
0068 trips {
0069 cpu_alert0: trip0 {
0070 temperature = <75000>;
0071 hysteresis = <2000>;
0072 type = "passive";
0073 };
0074
0075 cpu_alert1: trip1 {
0076 temperature = <80000>;
0077 hysteresis = <2000>;
0078 type = "passive";
0079 };
0080
0081 cpu_crit0: trip3 {
0082 temperature = <90000>;
0083 hysteresis = <2000>;
0084 type = "critical";
0085 };
0086
0087 fan_toggle0: trip4 {
0088 temperature = <65000>;
0089 hysteresis = <10000>;
0090 type = "active";
0091 };
0092 };
0093
0094 cooling-maps {
0095 map0 {
0096 trip = <&cpu_alert0>;
0097 cooling-device =
0098 <&A53_0 0 1>; /* Exclude highest OPP */
0099 };
0100
0101 map1 {
0102 trip = <&cpu_alert1>;
0103 cooling-device =
0104 <&A53_0 0 2>; /* Exclude two highest OPPs */
0105 };
0106
0107 map4 {
0108 trip = <&fan_toggle0>;
0109 cooling-device = <&fan 0 1>;
0110 };
0111 };
0112 };
0113
0114 &i2c1 {
0115 clock-frequency = <400000>;
0116 pinctrl-names = "default";
0117 pinctrl-0 = <&pinctrl_i2c1>;
0118 status = "okay";
0119
0120 pmic: pmic@4b {
0121 compatible = "rohm,bd71837";
0122 reg = <0x4b>;
0123 pinctrl-names = "default";
0124 pinctrl-0 = <&pinctrl_pmic>;
0125 #clock-cells = <0>;
0126 clocks = <&pmic_osc>;
0127 clock-output-names = "pmic_clk";
0128 interrupt-parent = <&gpio1>;
0129 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0130
0131 regulators {
0132 buck1: BUCK1 {
0133 regulator-name = "buck1";
0134 regulator-min-microvolt = <700000>;
0135 regulator-max-microvolt = <1300000>;
0136 regulator-boot-on;
0137 regulator-always-on;
0138 regulator-ramp-delay = <1250>;
0139 rohm,dvs-run-voltage = <900000>;
0140 rohm,dvs-idle-voltage = <900000>;
0141 rohm,dvs-suspend-voltage = <800000>;
0142 };
0143
0144 buck2: BUCK2 {
0145 regulator-name = "buck2";
0146 regulator-min-microvolt = <850000>;
0147 regulator-max-microvolt = <1000000>;
0148 regulator-boot-on;
0149 regulator-always-on;
0150 rohm,dvs-run-voltage = <1000000>;
0151 rohm,dvs-idle-voltage = <900000>;
0152 };
0153
0154 buck3: BUCK3 {
0155 regulator-name = "buck3";
0156 regulator-min-microvolt = <700000>;
0157 regulator-max-microvolt = <1300000>;
0158 regulator-boot-on;
0159 rohm,dvs-run-voltage = <900000>;
0160 };
0161
0162 buck4: BUCK4 {
0163 regulator-name = "buck4";
0164 regulator-min-microvolt = <700000>;
0165 regulator-max-microvolt = <1300000>;
0166 regulator-boot-on;
0167 regulator-always-on;
0168 rohm,dvs-run-voltage = <900000>;
0169 };
0170
0171 buck5: BUCK5 {
0172 regulator-name = "buck5";
0173 regulator-min-microvolt = <700000>;
0174 regulator-max-microvolt = <1350000>;
0175 regulator-boot-on;
0176 regulator-always-on;
0177 };
0178
0179 buck6: BUCK6 {
0180 regulator-name = "buck6";
0181 regulator-min-microvolt = <3000000>;
0182 regulator-max-microvolt = <3300000>;
0183 regulator-boot-on;
0184 regulator-always-on;
0185 };
0186
0187 buck7: BUCK7 {
0188 regulator-name = "buck7";
0189 regulator-min-microvolt = <1605000>;
0190 regulator-max-microvolt = <1995000>;
0191 regulator-boot-on;
0192 regulator-always-on;
0193 };
0194
0195 buck8: BUCK8 {
0196 regulator-name = "buck8";
0197 regulator-min-microvolt = <800000>;
0198 regulator-max-microvolt = <1400000>;
0199 regulator-boot-on;
0200 regulator-always-on;
0201 };
0202
0203 ldo1: LDO1 {
0204 regulator-name = "ldo1";
0205 regulator-min-microvolt = <3000000>;
0206 regulator-max-microvolt = <3300000>;
0207 regulator-boot-on;
0208 regulator-always-on;
0209 };
0210
0211 ldo2: LDO2 {
0212 regulator-name = "ldo2";
0213 regulator-min-microvolt = <900000>;
0214 regulator-max-microvolt = <900000>;
0215 regulator-boot-on;
0216 regulator-always-on;
0217 };
0218
0219 ldo3: LDO3 {
0220 regulator-name = "ldo3";
0221 regulator-min-microvolt = <1800000>;
0222 regulator-max-microvolt = <3300000>;
0223 regulator-boot-on;
0224 regulator-always-on;
0225 };
0226
0227 ldo4: LDO4 {
0228 regulator-name = "ldo4";
0229 regulator-min-microvolt = <900000>;
0230 regulator-max-microvolt = <1800000>;
0231 regulator-boot-on;
0232 regulator-always-on;
0233 };
0234
0235 ldo5: LDO5 {
0236 regulator-name = "ldo5";
0237 regulator-min-microvolt = <1800000>;
0238 regulator-max-microvolt = <3300000>;
0239 regulator-boot-on;
0240 regulator-always-on;
0241 };
0242
0243 ldo6: LDO6 {
0244 regulator-name = "ldo6";
0245 regulator-min-microvolt = <900000>;
0246 regulator-max-microvolt = <1800000>;
0247 regulator-boot-on;
0248 regulator-always-on;
0249 };
0250
0251 ldo7: LDO7 {
0252 regulator-name = "ldo7";
0253 regulator-min-microvolt = <1800000>;
0254 regulator-max-microvolt = <3300000>;
0255 regulator-boot-on;
0256 regulator-always-on;
0257 };
0258 };
0259 };
0260 };
0261
0262 &fec1 {
0263 pinctrl-names = "default";
0264 pinctrl-0 = <&pinctrl_fec1>;
0265 phy-mode = "rgmii-id";
0266 phy-handle = <ðphy0>;
0267 fsl,magic-packet;
0268 status = "okay";
0269
0270 mdio {
0271 #address-cells = <1>;
0272 #size-cells = <0>;
0273 ethphy0: ethernet-phy@0 {
0274 compatible = "ethernet-phy-ieee802.3-c22";
0275 reg = <0>;
0276 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
0277 reset-assert-us = <10000>;
0278 reset-deassert-us = <50000>;
0279 };
0280 };
0281 };
0282
0283 &uart1 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_uart1>;
0286 status = "okay";
0287 };
0288
0289 &usdhc1 {
0290 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0291 pinctrl-0 = <&pinctrl_usdhc1>;
0292 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0293 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0294 bus-width = <8>;
0295 non-removable;
0296 status = "okay";
0297 };
0298
0299 &usdhc2 {
0300 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0301 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0302 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0303 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0304 bus-width = <4>;
0305 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0306 vmmc-supply = <®_usdhc2_vmmc>;
0307 status = "okay";
0308 };
0309
0310 &usb3_phy0 {
0311 status = "okay";
0312 };
0313
0314 &usb_dwc3_0 {
0315 dr_mode = "otg";
0316 status = "okay";
0317 };
0318
0319 &usb3_phy1 {
0320 status = "okay";
0321 };
0322
0323 &usb_dwc3_1 {
0324 dr_mode = "host";
0325 status = "okay";
0326 };
0327
0328 &wdog1 {
0329 pinctrl-names = "default";
0330 pinctrl-0 = <&pinctrl_wdog>;
0331 fsl,ext-reset-output;
0332 status = "okay";
0333 };
0334
0335 &iomuxc {
0336 pinctrl_fec1: fec1grp {
0337 fsl,pins = <
0338 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0339 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
0340 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0341 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0342 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0343 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0344 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0345 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0346 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0347 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0348 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0349 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0350 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0351 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0352 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
0353 >;
0354 };
0355
0356 pinctrl_gpio_fan: gpiofangrp {
0357 fsl,pins = <
0358 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
0359 >;
0360 };
0361
0362 pinctrl_i2c1: i2c1grp {
0363 fsl,pins = <
0364 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
0365 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
0366 >;
0367 };
0368
0369 pinctrl_pmic: pmicirqgrp {
0370 fsl,pins = <
0371 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
0372 >;
0373 };
0374
0375 pinctrl_uart1: uart1grp {
0376 fsl,pins = <
0377 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
0378 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
0379 >;
0380 };
0381
0382 pinctrl_usdhc1: usdhc1grp {
0383 fsl,pins = <
0384 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
0385 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
0386 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
0387 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
0388 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
0389 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
0390 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
0391 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
0392 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
0393 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
0394 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
0395 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0396 >;
0397 };
0398
0399 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0400 fsl,pins = <
0401 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
0402 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
0403 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
0404 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
0405 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
0406 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
0407 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
0408 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
0409 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
0410 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
0411 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
0412 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0413 >;
0414 };
0415
0416 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0417 fsl,pins = <
0418 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
0419 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
0420 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
0421 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
0422 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
0423 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
0424 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
0425 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
0426 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
0427 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
0428 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
0429 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0430 >;
0431 };
0432
0433 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0434 fsl,pins = <
0435 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
0436 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
0437 >;
0438 };
0439
0440 pinctrl_usdhc2: usdhc2grp {
0441 fsl,pins = <
0442 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
0443 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
0444 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
0445 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
0446 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
0447 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
0448 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0449 >;
0450 };
0451
0452 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0453 fsl,pins = <
0454 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
0455 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
0456 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
0457 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
0458 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
0459 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
0460 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0461 >;
0462 };
0463
0464 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0465 fsl,pins = <
0466 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
0467 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
0468 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
0469 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
0470 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
0471 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
0472 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0473 >;
0474 };
0475
0476 pinctrl_wdog: wdoggrp {
0477 fsl,pins = <
0478 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0479 >;
0480 };
0481 };
