0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2018 Boundary Devices
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/input/input.h>
0009 #include "imx8mq.dtsi"
0010
0011 / {
0012 model = "Boundary Devices i.MX8MQ Nitrogen8M";
0013 compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
0014
0015 chosen {
0016 stdout-path = "serial0:115200n8";
0017 };
0018
0019 memory@40000000 {
0020 device_type = "memory";
0021 reg = <0x00000000 0x40000000 0 0x80000000>;
0022 };
0023
0024 gpio-keys {
0025 compatible = "gpio-keys";
0026 pinctrl-names = "default";
0027 pinctrl-0 = <&pinctrl_gpio_keys>;
0028
0029 button-power {
0030 label = "Power Button";
0031 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
0032 linux,code = <KEY_POWER>;
0033 wakeup-source;
0034 };
0035 };
0036
0037 hdmi-connector {
0038 compatible = "hdmi-connector";
0039 ddc-i2c-bus = <&ddc_i2c_bus>;
0040 label = "hdmi";
0041 type = "a";
0042
0043 port {
0044 hdmi_connector_in: endpoint {
0045 remote-endpoint = <<8912_out>;
0046 };
0047 };
0048 };
0049
0050 reg_usb_otg_vbus: regulator-usb-otg-vbus {
0051 compatible = "regulator-fixed";
0052 pinctrl-names = "default";
0053 pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
0054 regulator-name = "usb_otg_vbus";
0055 regulator-min-microvolt = <5000000>;
0056 regulator-max-microvolt = <5000000>;
0057 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0058 enable-active-high;
0059 };
0060
0061 reg_vref_0v9: regulator-vref-0v9 {
0062 compatible = "regulator-fixed";
0063 regulator-name = "vref-0v9";
0064 regulator-min-microvolt = <900000>;
0065 regulator-max-microvolt = <900000>;
0066 };
0067
0068 reg_vref_1v8: regulator-vref-1v8 {
0069 compatible = "regulator-fixed";
0070 regulator-name = "vref-1v8";
0071 regulator-min-microvolt = <1800000>;
0072 regulator-max-microvolt = <1800000>;
0073 };
0074
0075 reg_vref_2v5: regulator-vref-2v5 {
0076 compatible = "regulator-fixed";
0077 regulator-name = "vref-2v5";
0078 regulator-min-microvolt = <2500000>;
0079 regulator-max-microvolt = <2500000>;
0080 };
0081
0082 reg_vref_3v3: regulator-vref-3v3 {
0083 compatible = "regulator-fixed";
0084 regulator-name = "vref-3v3";
0085 regulator-min-microvolt = <3300000>;
0086 regulator-max-microvolt = <3300000>;
0087 };
0088
0089 reg_vref_5v: regulator-vref-5v {
0090 compatible = "regulator-fixed";
0091 regulator-name = "vref-5v";
0092 regulator-min-microvolt = <5000000>;
0093 regulator-max-microvolt = <5000000>;
0094 };
0095 };
0096
0097 &dphy {
0098 status = "okay";
0099 };
0100
0101 &fec1 {
0102 pinctrl-names = "default";
0103 pinctrl-0 = <&pinctrl_fec1>;
0104 phy-mode = "rgmii-id";
0105 phy-handle = <ðphy0>;
0106 fsl,magic-packet;
0107 status = "okay";
0108
0109 mdio {
0110 #address-cells = <1>;
0111 #size-cells = <0>;
0112
0113 ethphy0: ethernet-phy@4 {
0114 compatible = "ethernet-phy-ieee802.3-c22";
0115 reg = <4>;
0116 interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
0117 };
0118 };
0119 };
0120
0121 /* Release reset of the USB Host HUB */
0122 &gpio1 {
0123 usb-host-reset-hog {
0124 gpio-hog;
0125 gpios = <14 GPIO_ACTIVE_HIGH>;
0126 output-high;
0127 };
0128 };
0129
0130 &i2c1 {
0131 clock-frequency = <400000>;
0132 pinctrl-names = "default";
0133 pinctrl-0 = <&pinctrl_i2c1>;
0134 status = "okay";
0135
0136 i2cmux@70 {
0137 compatible = "nxp,pca9546";
0138 pinctrl-names = "default";
0139 pinctrl-0 = <&pinctrl_i2c1_pca9546>;
0140 reg = <0x70>;
0141 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
0142 #address-cells = <1>;
0143 #size-cells = <0>;
0144
0145 i2c1a: i2c1@0 {
0146 reg = <0>;
0147 #address-cells = <1>;
0148 #size-cells = <0>;
0149
0150 reg_arm_dram: regulator@60 {
0151 compatible = "fcs,fan53555";
0152 pinctrl-names = "default";
0153 pinctrl-0 = <&pinctrl_reg_arm_dram>;
0154 reg = <0x60>;
0155 regulator-min-microvolt = <900000>;
0156 regulator-max-microvolt = <1000000>;
0157 regulator-always-on;
0158 vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
0159 };
0160 };
0161
0162 i2c1b: i2c1@1 {
0163 reg = <1>;
0164 #address-cells = <1>;
0165 #size-cells = <0>;
0166
0167 reg_dram_1p1v: regulator@60 {
0168 compatible = "fcs,fan53555";
0169 pinctrl-names = "default";
0170 pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
0171 reg = <0x60>;
0172 regulator-min-microvolt = <1100000>;
0173 regulator-max-microvolt = <1100000>;
0174 regulator-always-on;
0175 vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
0176 };
0177 };
0178
0179 i2c1c: i2c1@2 {
0180 reg = <2>;
0181 #address-cells = <1>;
0182 #size-cells = <0>;
0183
0184 reg_soc_gpu_vpu: regulator@60 {
0185 compatible = "fcs,fan53555";
0186 pinctrl-names = "default";
0187 pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
0188 reg = <0x60>;
0189 regulator-min-microvolt = <900000>;
0190 regulator-max-microvolt = <1000000>;
0191 regulator-always-on;
0192 vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
0193 };
0194 };
0195
0196 i2c1d: i2c1@3 {
0197 reg = <3>;
0198 #address-cells = <1>;
0199 #size-cells = <0>;
0200
0201 rtc@68 {
0202 compatible = "microcrystal,rv4162";
0203 pinctrl-names = "default";
0204 pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
0205 reg = <0x68>;
0206 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
0207 wakeup-source;
0208 };
0209 };
0210 };
0211 };
0212
0213 &i2c4 {
0214 clock-frequency = <100000>;
0215 pinctrl-names = "default";
0216 pinctrl-0 = <&pinctrl_i2c4>;
0217 status = "okay";
0218
0219 pca9546: i2cmux@70 {
0220 compatible = "nxp,pca9546";
0221 reg = <0x70>;
0222 #address-cells = <1>;
0223 #size-cells = <0>;
0224
0225 i2c4@0 {
0226 reg = <0>;
0227 #address-cells = <1>;
0228 #size-cells = <0>;
0229 clock-frequency = <100000>;
0230
0231 hdmi-bridge@48 {
0232 compatible = "lontium,lt8912b";
0233 reg = <0x48> ;
0234 reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;
0235
0236 ports {
0237 #address-cells = <1>;
0238 #size-cells = <0>;
0239
0240 port@0 {
0241 reg = <0>;
0242
0243 hdmi_out_in: endpoint {
0244 data-lanes = <1 2 3 4>;
0245 remote-endpoint = <&mipi_dsi_out>;
0246 };
0247 };
0248
0249 port@1 {
0250 reg = <1>;
0251
0252 lt8912_out: endpoint {
0253 remote-endpoint = <&hdmi_connector_in>;
0254 };
0255 };
0256 };
0257 };
0258 };
0259
0260 ddc_i2c_bus: i2c4@1 {
0261 reg = <1>;
0262 #address-cells = <1>;
0263 #size-cells = <0>;
0264 clock-frequency = <100000>;
0265 };
0266
0267 i2c4@3 {
0268 reg = <3>;
0269 #address-cells = <1>;
0270 #size-cells = <0>;
0271 clock-frequency = <100000>;
0272
0273 max7323: gpio-expander@68 {
0274 compatible = "maxim,max7323";
0275 pinctrl-names = "default";
0276 pinctrl-0 = <&pinctrl_max7323>;
0277 gpio-controller;
0278 reg = <0x68>;
0279 #gpio-cells = <2>;
0280 };
0281 };
0282 };
0283 };
0284
0285 &lcdif {
0286 status = "okay";
0287 };
0288
0289 &mipi_dsi {
0290 #address-cells = <1>;
0291 #size-cells = <0>;
0292 status = "okay";
0293
0294 ports {
0295 port@1 {
0296 reg = <1>;
0297
0298 mipi_dsi_out: endpoint {
0299 remote-endpoint = <&hdmi_out_in>;
0300 };
0301 };
0302 };
0303 };
0304
0305 &uart1 { /* console */
0306 pinctrl-names = "default";
0307 pinctrl-0 = <&pinctrl_uart1>;
0308 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
0309 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
0310 status = "okay";
0311 };
0312
0313 &uart2 {
0314 pinctrl-names = "default";
0315 pinctrl-0 = <&pinctrl_uart2>;
0316 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
0317 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
0318 status = "okay";
0319 };
0320
0321 &usb_dwc3_0 {
0322 dr_mode = "otg";
0323 pinctrl-names = "default";
0324 pinctrl-0 = <&pinctrl_usb3_0>;
0325 status = "okay";
0326 };
0327
0328 &usb3_phy0 {
0329 vbus-supply = <®_usb_otg_vbus>;
0330 status = "okay";
0331 };
0332
0333 &usb_dwc3_1 {
0334 dr_mode = "host";
0335 status = "okay";
0336 };
0337
0338 &usb3_phy1 {
0339 pinctrl-names = "default";
0340 pinctrl-0 = <&pinctrl_usb3_1>;
0341 status = "okay";
0342 };
0343
0344 &usdhc1 {
0345 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
0346 assigned-clock-rates = <400000000>;
0347 bus-width = <8>;
0348 pinctrl-names = "default";
0349 pinctrl-0 = <&pinctrl_usdhc1>;
0350 non-removable;
0351 vmmc-supply = <®_vref_1v8>;
0352 status = "okay";
0353 };
0354
0355 &wdog1 {
0356 pinctrl-names = "default";
0357 pinctrl-0 = <&pinctrl_wdog>;
0358 fsl,ext-reset-output;
0359 status = "okay";
0360 };
0361
0362 &iomuxc {
0363 pinctrl-names = "default";
0364 pinctrl-0 = <&pinctrl_hog>;
0365
0366 pinctrl_hog: hoggrp {
0367 fsl,pins = <
0368 /* J17 connector, odd */
0369 MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
0370 MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
0371 MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
0372 MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
0373 MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
0374 MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
0375 MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
0376 MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
0377 MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
0378 MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
0379 MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
0380 MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
0381 MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
0382 MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
0383 MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
0384 MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
0385
0386 /* J17 connector, even */
0387 MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
0388 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
0389 MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
0390 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
0391 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
0392
0393 /* J18 connector, odd */
0394 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
0395 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
0396 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
0397 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
0398 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
0399 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
0400
0401 /* J18 connector, even */
0402 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
0403 MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
0404 MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
0405 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
0406 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
0407 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
0408 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
0409
0410 /* J13 Pin 2, WL_WAKE */
0411 MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
0412 /* J13 Pin 4, WL_IRQ, not needed for Silex */
0413 MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
0414 /* J13 pin 9, unused */
0415 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
0416 /* J13 Pin 41, BT_CLK_REQ */
0417 MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
0418 /* J13 Pin 42, BT_HOST_WAKE */
0419 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
0420
0421 /* Clock for both CSI1 and CSI2 */
0422 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
0423 /* test points */
0424 MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
0425 >;
0426 };
0427
0428 pinctrl_fec1: fec1grp {
0429 fsl,pins = <
0430 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0431 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
0432 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0433 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0434 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0435 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0436 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0437 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0438 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0439 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0440 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0441 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0442 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0443 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0444 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
0445 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
0446 >;
0447 };
0448
0449 pinctrl_gpio_keys: gpio-keysgrp {
0450 fsl,pins = <
0451 MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
0452 >;
0453 };
0454
0455
0456 pinctrl_i2c1: i2c1grp {
0457 fsl,pins = <
0458 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
0459 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
0460 >;
0461 };
0462
0463 pinctrl_i2c1_pca9546: i2c1-pca9546grp {
0464 fsl,pins = <
0465 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
0466 >;
0467 };
0468
0469 pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
0470 fsl,pins = <
0471 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
0472 >;
0473 };
0474
0475 pinctrl_i2c4: i2c4grp {
0476 fsl,pins = <
0477 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
0478 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
0479 >;
0480 };
0481
0482 pinctrl_max7323: max7323grp {
0483 fsl,pins = <
0484 MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
0485 >;
0486 };
0487
0488 pinctrl_reg_arm_dram: reg-arm-dramgrp {
0489 fsl,pins = <
0490 MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
0491 >;
0492 };
0493
0494 pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp {
0495 fsl,pins = <
0496 MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
0497 >;
0498 };
0499
0500 pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp {
0501 fsl,pins = <
0502 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
0503 >;
0504 };
0505
0506 pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
0507 fsl,pins = <
0508 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
0509 >;
0510 };
0511
0512 pinctrl_uart1: uart1grp {
0513 fsl,pins = <
0514 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
0515 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
0516 >;
0517 };
0518
0519 pinctrl_uart2: uart2grp {
0520 fsl,pins = <
0521 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
0522 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
0523 >;
0524 };
0525
0526 pinctrl_usb3_0: usb3-0grp {
0527 fsl,pins = <
0528 MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
0529 >;
0530 };
0531
0532 pinctrl_usb3_1: usb3-1grp {
0533 fsl,pins = <
0534 MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
0535 >;
0536 };
0537
0538 pinctrl_usdhc1: usdhc1grp {
0539 fsl,pins = <
0540 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
0541 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
0542 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
0543 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
0544 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
0545 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
0546 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
0547 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
0548 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
0549 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
0550 MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
0551 >;
0552 };
0553
0554 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0555 fsl,pins = <
0556 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
0557 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
0558 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
0559 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
0560 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
0561 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
0562 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
0563 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
0564 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
0565 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
0566 >;
0567 };
0568
0569 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0570 fsl,pins = <
0571 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
0572 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
0573 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
0574 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
0575 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
0576 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
0577 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
0578 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
0579 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
0580 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
0581 >;
0582 };
0583
0584 pinctrl_wdog: wdoggrp {
0585 fsl,pins = <
0586 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0587 >;
0588 };
0589 };
