0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2018 Boundary Devices
0004 * Copyright 2021 Lucas Stach <dev@lynxeye.de>
0005 */
0006
0007 #include "imx8mq.dtsi"
0008
0009 / {
0010 model = "Boundary Devices i.MX8MQ Nitrogen8M";
0011 compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
0012
0013 chosen {
0014 stdout-path = &uart1;
0015 };
0016
0017 reg_1p8v: regulator-fixed-1v8 {
0018 compatible = "regulator-fixed";
0019 regulator-name = "1P8V";
0020 regulator-min-microvolt = <1800000>;
0021 regulator-max-microvolt = <1800000>;
0022 };
0023
0024 reg_snvs: regulator-fixed-snvs {
0025 compatible = "regulator-fixed";
0026 regulator-name = "VDD_SNVS";
0027 regulator-min-microvolt = <3300000>;
0028 regulator-max-microvolt = <3300000>;
0029 };
0030 };
0031
0032 &{/opp-table/opp-800000000} {
0033 opp-microvolt = <1000000>;
0034 };
0035
0036 &{/opp-table/opp-1000000000} {
0037 opp-microvolt = <1000000>;
0038 };
0039
0040 &A53_0 {
0041 cpu-supply = <®_arm_dram>;
0042 };
0043
0044 &A53_1 {
0045 cpu-supply = <®_arm_dram>;
0046 };
0047
0048 &A53_2 {
0049 cpu-supply = <®_arm_dram>;
0050 };
0051
0052 &A53_3 {
0053 cpu-supply = <®_arm_dram>;
0054 };
0055
0056 &fec1 {
0057 pinctrl-names = "default";
0058 pinctrl-0 = <&pinctrl_fec1>;
0059 phy-mode = "rgmii-id";
0060 phy-handle = <ðphy0>;
0061 fsl,magic-packet;
0062
0063 mdio {
0064 #address-cells = <1>;
0065 #size-cells = <0>;
0066
0067 ethphy0: ethernet-phy@4 {
0068 compatible = "ethernet-phy-ieee802.3-c22";
0069 reg = <4>;
0070 interrupt-parent = <&gpio1>;
0071 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
0072 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
0073 reset-assert-us = <10000>;
0074 reset-deassert-us = <300>;
0075 };
0076 };
0077 };
0078
0079 &i2c1 {
0080 clock-frequency = <400000>;
0081 pinctrl-names = "default";
0082 pinctrl-0 = <&pinctrl_i2c1>;
0083 status = "okay";
0084
0085 i2c-mux@70 {
0086 compatible = "nxp,pca9546";
0087 pinctrl-names = "default";
0088 pinctrl-0 = <&pinctrl_i2c1_pca9546>;
0089 reg = <0x70>;
0090 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
0091 #address-cells = <1>;
0092 #size-cells = <0>;
0093
0094 i2c1a: i2c@0 {
0095 reg = <0>;
0096 #address-cells = <1>;
0097 #size-cells = <0>;
0098
0099 reg_arm_dram: regulator@60 {
0100 compatible = "fcs,fan53555";
0101 reg = <0x60>;
0102 regulator-name = "VDD_ARM_DRAM_1V";
0103 regulator-min-microvolt = <1000000>;
0104 regulator-max-microvolt = <1000000>;
0105 regulator-always-on;
0106 };
0107 };
0108
0109 i2c1b: i2c@1 {
0110 reg = <1>;
0111 #address-cells = <1>;
0112 #size-cells = <0>;
0113
0114 reg_dram_1p1v: regulator@60 {
0115 compatible = "fcs,fan53555";
0116 reg = <0x60>;
0117 regulator-name = "NVCC_DRAM_1P1V";
0118 regulator-min-microvolt = <1100000>;
0119 regulator-max-microvolt = <1100000>;
0120 regulator-always-on;
0121 };
0122 };
0123
0124 i2c1c: i2c@2 {
0125 reg = <2>;
0126 #address-cells = <1>;
0127 #size-cells = <0>;
0128
0129 reg_soc_gpu_vpu: regulator@60 {
0130 compatible = "fcs,fan53555";
0131 reg = <0x60>;
0132 regulator-name = "VDD_SOC_GPU_VPU";
0133 regulator-min-microvolt = <900000>;
0134 regulator-max-microvolt = <900000>;
0135 regulator-always-on;
0136 };
0137 };
0138
0139 i2c1d: i2c@3 {
0140 reg = <3>;
0141 #address-cells = <1>;
0142 #size-cells = <0>;
0143 };
0144 };
0145 };
0146
0147 &pgc_gpu {
0148 power-supply = <®_soc_gpu_vpu>;
0149 };
0150
0151 &pgc_vpu {
0152 power-supply = <®_soc_gpu_vpu>;
0153 };
0154
0155 &uart1 {
0156 pinctrl-names = "default";
0157 pinctrl-0 = <&pinctrl_uart1>;
0158 status = "okay";
0159 };
0160
0161 &usdhc1 {
0162 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
0163 assigned-clock-rates = <400000000>;
0164 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0165 pinctrl-0 = <&pinctrl_usdhc1>;
0166 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0167 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0168 vqmmc-supply = <®_1p8v>;
0169 vmmc-supply = <®_snvs>;
0170 bus-width = <8>;
0171 non-removable;
0172 no-mmc-hs400;
0173 no-sdio;
0174 no-sd;
0175 status = "okay";
0176 };
0177
0178 &wdog1 {
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&pinctrl_wdog>;
0181 fsl,ext-reset-output;
0182 status = "okay";
0183 };
0184
0185 &iomuxc {
0186 pinctrl_fec1: fec1grp {
0187 fsl,pins = <
0188 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0189 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
0190 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0191 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0192 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0193 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0194 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0195 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0196 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0197 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1
0198 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0199 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0200 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0201 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1
0202 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1
0203 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41
0204 >;
0205 };
0206
0207 pinctrl_i2c1: i2c1grp {
0208 fsl,pins = <
0209 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022
0210 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022
0211 >;
0212 };
0213
0214 pinctrl_i2c1_pca9546: i2c1-pca9546grp {
0215 fsl,pins = <
0216 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
0217 >;
0218 };
0219
0220 pinctrl_uart1: uart1grp {
0221 fsl,pins = <
0222 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
0223 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
0224 >;
0225 };
0226
0227 pinctrl_usdhc1: usdhc1grp {
0228 fsl,pins = <
0229 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
0230 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
0231 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
0232 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
0233 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
0234 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
0235 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
0236 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
0237 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
0238 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
0239 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0240 >;
0241 };
0242
0243 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
0244 fsl,pins = <
0245 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
0246 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
0247 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
0248 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
0249 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
0250 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
0251 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
0252 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
0253 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
0254 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
0255 >;
0256 };
0257
0258 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
0259 fsl,pins = <
0260 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
0261 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
0262 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
0263 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
0264 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
0265 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
0266 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
0267 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
0268 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
0269 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
0270 >;
0271 };
0272
0273 pinctrl_wdog: wdoggrp {
0274 fsl,pins = <
0275 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0276 >;
0277 };
0278 };
