arm64/freescale/imx8mq-mnt-reform2.dts

0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002
0003 /*
0004  * Copyright 2019-2021 MNT Research GmbH
0005  * Copyright 2021 Lucas Stach <dev@lynxeye.de>
0006  */
0007
0008 /dts-v1/;
0009
0010 #include "imx8mq-nitrogen-som.dtsi"
0011
0012 / {
0013         model = "MNT Reform 2";
0014         compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
0015         chassis-type = "laptop";
0016
0017         backlight: backlight {
0018                 compatible = "pwm-backlight";
0019                 pinctrl-names = "default";
0020                 pinctrl-0 = <&pinctrl_backlight>;
0021                 pwms = <&pwm2 0 10000 0>;
0022                 power-supply = <&reg_main_usb>;
0023                 enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
0024                 brightness-levels = <0 32 64 128 160 200 255>;
0025                 default-brightness-level = <6>;
0026         };
0027
0028         panel {
0029                 compatible = "innolux,n125hce-gn1", "simple-panel";
0030                 power-supply = <&reg_main_3v3>;
0031                 backlight = <&backlight>;
0032                 no-hpd;
0033
0034                 port {
0035                         panel_in: endpoint {
0036                                 remote-endpoint = <&edp_bridge_out>;
0037                         };
0038                 };
0039         };
0040
0041         pcie1_refclk: clock-pcie1-refclk {
0042                 compatible = "fixed-clock";
0043                 #clock-cells = <0>;
0044                 clock-frequency = <100000000>;
0045         };
0046
0047         reg_main_5v: regulator-main-5v {
0048                 compatible = "regulator-fixed";
0049                 regulator-name = "5V";
0050                 regulator-min-microvolt = <5000000>;
0051                 regulator-max-microvolt = <5000000>;
0052         };
0053
0054         reg_main_3v3: regulator-main-3v3 {
0055                 compatible = "regulator-fixed";
0056                 regulator-name = "3V3";
0057                 regulator-min-microvolt = <3300000>;
0058                 regulator-max-microvolt = <3300000>;
0059         };
0060
0061         reg_main_usb: regulator-main-usb {
0062                 compatible = "regulator-fixed";
0063                 regulator-name = "USB_PWR";
0064                 regulator-min-microvolt = <5000000>;
0065                 regulator-max-microvolt = <5000000>;
0066                 vin-supply = <&reg_main_5v>;
0067         };
0068
0069         reg_main_1v8: regulator-main-1v8 {
0070                 compatible = "regulator-fixed";
0071                 regulator-name = "1V8";
0072                 regulator-min-microvolt = <1800000>;
0073                 regulator-max-microvolt = <1800000>;
0074                 vin-supply = <&reg_main_3v3>;
0075         };
0076
0077         reg_main_1v2: regulator-main-1v2 {
0078                 compatible = "regulator-fixed";
0079                 regulator-name = "1V2";
0080                 regulator-min-microvolt = <1200000>;
0081                 regulator-max-microvolt = <1200000>;
0082                 vin-supply = <&reg_main_5v>;
0083         };
0084
0085         sound {
0086                 compatible = "fsl,imx-audio-wm8960";
0087                 audio-cpu = <&sai2>;
0088                 audio-codec = <&wm8960>;
0089                 audio-routing =
0090                         "Headphone Jack", "HP_L",
0091                         "Headphone Jack", "HP_R",
0092                         "Ext Spk", "SPK_LP",
0093                         "Ext Spk", "SPK_LN",
0094                         "Ext Spk", "SPK_RP",
0095                         "Ext Spk", "SPK_RN",
0096                         "LINPUT1", "Mic Jack",
0097                         "Mic Jack", "MICB",
0098                         "LINPUT2", "Line In Jack",
0099                         "RINPUT2", "Line In Jack";
0100                 model = "wm8960-audio";
0101         };
0102 };
0103
0104 &dphy {
0105         assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
0106         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
0107         assigned-clock-rates = <25000000>;
0108         status = "okay";
0109 };
0110
0111 &fec1 {
0112         status = "okay";
0113 };
0114
0115 &i2c3 {
0116         pinctrl-names = "default";
0117         pinctrl-0 = <&pinctrl_i2c3>;
0118         status = "okay";
0119
0120         wm8960: codec@1a {
0121                 compatible = "wlf,wm8960";
0122                 reg = <0x1a>;
0123                 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
0124                 clock-names = "mclk";
0125                 #sound-dai-cells = <0>;
0126         };
0127
0128         rtc@68 {
0129                 compatible = "nxp,pcf8523";
0130                 reg = <0x68>;
0131         };
0132 };
0133
0134 &i2c4 {
0135         pinctrl-names = "default";
0136         pinctrl-0 = <&pinctrl_i2c4>;
0137         clock-frequency = <400000>;
0138         status = "okay";
0139
0140         edp_bridge: bridge@2c {
0141                 compatible = "ti,sn65dsi86";
0142                 pinctrl-names = "default";
0143                 pinctrl-0 = <&pinctrl_edp_bridge>;
0144                 reg = <0x2c>;
0145                 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
0146                 vccio-supply = <&reg_main_1v8>;
0147                 vpll-supply = <&reg_main_1v8>;
0148                 vcca-supply = <&reg_main_1v2>;
0149                 vcc-supply = <&reg_main_1v2>;
0150
0151                 ports {
0152                         #address-cells = <1>;
0153                         #size-cells = <0>;
0154
0155                         port@0 {
0156                                 reg = <0>;
0157
0158                                 edp_bridge_in: endpoint {
0159                                         remote-endpoint = <&mipi_dsi_out>;
0160                                 };
0161                         };
0162
0163                         port@1 {
0164                                 reg = <1>;
0165
0166                                 edp_bridge_out: endpoint {
0167                                         remote-endpoint = <&panel_in>;
0168                                 };
0169                         };
0170                 };
0171         };
0172 };
0173
0174 &lcdif {
0175         assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
0176         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
0177         /delete-property/assigned-clock-rates;
0178         status = "okay";
0179 };
0180
0181 &mipi_dsi {
0182         status = "okay";
0183
0184         ports {
0185                 port@1 {
0186                         reg = <1>;
0187
0188                         mipi_dsi_out: endpoint {
0189                                 remote-endpoint = <&edp_bridge_in>;
0190                         };
0191                 };
0192         };
0193 };
0194
0195 &pcie1 {
0196         pinctrl-names = "default";
0197         pinctrl-0 = <&pinctrl_pcie1>;
0198         reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
0199         clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
0200                  <&clk IMX8MQ_CLK_PCIE2_AUX>,
0201                  <&clk IMX8MQ_CLK_PCIE2_PHY>,
0202                  <&pcie1_refclk>;
0203         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
0204         status = "okay";
0205 };
0206
0207 &pwm2 {
0208         pinctrl-names = "default";
0209         pinctrl-0 = <&pinctrl_pwm2>;
0210         status = "okay";
0211 };
0212
0213
0214 &reg_1p8v {
0215         vin-supply = <&reg_main_5v>;
0216 };
0217
0218 &reg_snvs {
0219         vin-supply = <&reg_main_5v>;
0220 };
0221
0222 &reg_arm_dram {
0223         vin-supply = <&reg_main_5v>;
0224 };
0225
0226 &reg_dram_1p1v {
0227         vin-supply = <&reg_main_5v>;
0228 };
0229
0230 &reg_soc_gpu_vpu {
0231         vin-supply = <&reg_main_5v>;
0232 };
0233
0234 &sai2 {
0235         pinctrl-names = "default";
0236         pinctrl-0 = <&pinctrl_sai2>;
0237         assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
0238         assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
0239         assigned-clock-rates = <25000000>;
0240         fsl,sai-mclk-direction-output;
0241         fsl,sai-asynchronous;
0242         status = "okay";
0243 };
0244
0245 &snvs_rtc {
0246         status = "disabled";
0247 };
0248
0249 &uart2 {
0250         pinctrl-names = "default";
0251         pinctrl-0 = <&pinctrl_uart2>;
0252         status = "okay";
0253 };
0254
0255 &usb3_phy0 {
0256         vbus-supply = <&reg_main_usb>;
0257         status = "okay";
0258 };
0259
0260 &usb3_phy1 {
0261         vbus-supply = <&reg_main_usb>;
0262         status = "okay";
0263 };
0264
0265 &usb_dwc3_0 {
0266         dr_mode = "host";
0267         status = "okay";
0268 };
0269
0270 &usb_dwc3_1 {
0271         dr_mode = "host";
0272         status = "okay";
0273 };
0274
0275 &usdhc2 {
0276         assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
0277         assigned-clock-rates = <200000000>;
0278         pinctrl-names = "default";
0279         pinctrl-0 = <&pinctrl_usdhc2>;
0280         vqmmc-supply = <&reg_main_3v3>;
0281         vmmc-supply = <&reg_main_3v3>;
0282         bus-width = <4>;
0283         status = "okay";
0284 };
0285
0286 &iomuxc {
0287         pinctrl_backlight: backlightgrp {
0288                 fsl,pins = <
0289                         MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x3
0290                 >;
0291         };
0292
0293         pinctrl_edp_bridge: edpbridgegrp {
0294                 fsl,pins = <
0295                         MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20                0x1
0296                 >;
0297         };
0298
0299         pinctrl_i2c3: i2c3grp {
0300                 fsl,pins = <
0301                         MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                  0x40000022
0302                         MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                  0x40000022
0303                 >;
0304         };
0305
0306         pinctrl_i2c4: i2c4grp {
0307                 fsl,pins = <
0308                         MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                  0x40000022
0309                         MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                  0x40000022
0310                 >;
0311         };
0312
0313         pinctrl_pcie1: pcie1grp {
0314                 fsl,pins = <
0315                         MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23               0x16
0316                 >;
0317         };
0318
0319         pinctrl_pwm2: pwm2grp {
0320                 fsl,pins = <
0321                         MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT                  0x3
0322                 >;
0323         };
0324
0325         pinctrl_sai2: sai2grp {
0326                 fsl,pins = <
0327                         MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0            0xd6
0328                         MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC             0xd6
0329                         MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK              0xd6
0330                         MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC             0xd6
0331                         MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK              0xd6
0332                         MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK                0xd6
0333                         MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0            0xd6
0334                 >;
0335         };
0336
0337         pinctrl_uart2: uart2grp {
0338                 fsl,pins = <
0339                         MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX             0x45
0340                         MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX             0x45
0341                 >;
0342         };
0343
0344         pinctrl_usdhc2: usdhc2grp {
0345                 fsl,pins = <
0346                         MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B               0x0
0347                         MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                 0x83
0348                         MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                 0xc3
0349                         MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0             0xc3
0350                         MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1             0xc3
0351                         MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2             0xc3
0352                         MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3             0xc3
0353                 >;
0354         };
0355 };