0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Device Tree File for the Kontron pitx-imx8m board.
0004 *
0005 * Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
0006 */
0007
0008 /dts-v1/;
0009
0010 #include "imx8mq.dtsi"
0011 #include <dt-bindings/net/ti-dp83867.h>
0012
0013 / {
0014 model = "Kontron pITX-imx8m";
0015 compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
0016
0017 aliases {
0018 i2c0 = &i2c1;
0019 i2c1 = &i2c2;
0020 i2c2 = &i2c3;
0021 mmc0 = &usdhc1;
0022 mmc1 = &usdhc2;
0023 serial0 = &uart1;
0024 serial1 = &uart2;
0025 serial2 = &uart3;
0026 spi0 = &qspi0;
0027 spi1 = &ecspi2;
0028 };
0029
0030 chosen {
0031 stdout-path = "serial2:115200n8";
0032 };
0033
0034 pcie0_refclk: pcie0-clock {
0035 compatible = "fixed-clock";
0036 #clock-cells = <0>;
0037 clock-frequency = <100000000>;
0038 };
0039
0040 pcie1_refclk: pcie1-clock {
0041 compatible = "fixed-clock";
0042 #clock-cells = <0>;
0043 clock-frequency = <100000000>;
0044 };
0045
0046 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
0047 compatible = "regulator-fixed";
0048 pinctrl-names = "default";
0049 pinctrl-0 = <&pinctrl_reg_usdhc2>;
0050 regulator-name = "V_3V3_SD";
0051 regulator-min-microvolt = <3300000>;
0052 regulator-max-microvolt = <3300000>;
0053 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0054 off-on-delay-us = <20000>;
0055 enable-active-high;
0056 };
0057 };
0058
0059 &ecspi2 {
0060 #address-cells = <1>;
0061 #size-cells = <0>;
0062 pinctrl-names = "default";
0063 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
0064 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0065 status = "okay";
0066
0067 tpm@0 {
0068 compatible = "infineon,slb9670";
0069 reg = <0>;
0070 spi-max-frequency = <43000000>;
0071 };
0072 };
0073
0074 &fec1 {
0075 pinctrl-names = "default";
0076 pinctrl-0 = <&pinctrl_fec1>;
0077 phy-mode = "rgmii-id";
0078 phy-handle = <ðphy0>;
0079 fsl,magic-packet;
0080 status = "okay";
0081
0082 mdio {
0083 #address-cells = <1>;
0084 #size-cells = <0>;
0085
0086 ethphy0: ethernet-phy@0 {
0087 compatible = "ethernet-phy-ieee802.3-c22";
0088 reg = <0>;
0089 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0090 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
0091 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0092 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
0093 reset-assert-us = <10>;
0094 reset-deassert-us = <280>;
0095 };
0096 };
0097 };
0098
0099 &i2c1 {
0100 clock-frequency = <400000>;
0101 pinctrl-names = "default";
0102 pinctrl-0 = <&pinctrl_i2c1>;
0103 status = "okay";
0104
0105 pmic@8 {
0106 compatible = "fsl,pfuze100";
0107 fsl,pfuze-support-disable-sw;
0108 reg = <0x8>;
0109
0110 regulators {
0111 sw1a_reg: sw1ab {
0112 regulator-name = "V_0V9_GPU";
0113 regulator-min-microvolt = <825000>;
0114 regulator-max-microvolt = <1100000>;
0115 };
0116
0117 sw1c_reg: sw1c {
0118 regulator-name = "V_0V9_VPU";
0119 regulator-min-microvolt = <825000>;
0120 regulator-max-microvolt = <1100000>;
0121 };
0122
0123 sw2_reg: sw2 {
0124 regulator-name = "V_1V1_NVCC_DRAM";
0125 regulator-min-microvolt = <1100000>;
0126 regulator-max-microvolt = <1100000>;
0127 regulator-always-on;
0128 };
0129
0130 sw3a_reg: sw3ab {
0131 regulator-name = "V_1V0_DRAM";
0132 regulator-min-microvolt = <825000>;
0133 regulator-max-microvolt = <1100000>;
0134 regulator-always-on;
0135 };
0136
0137 sw4_reg: sw4 {
0138 regulator-name = "V_1V8_S0";
0139 regulator-min-microvolt = <1800000>;
0140 regulator-max-microvolt = <1800000>;
0141 regulator-always-on;
0142 };
0143
0144 swbst_reg: swbst {
0145 regulator-name = "NC";
0146 regulator-min-microvolt = <5000000>;
0147 regulator-max-microvolt = <5150000>;
0148 };
0149
0150 snvs_reg: vsnvs {
0151 regulator-name = "V_0V9_SNVS";
0152 regulator-min-microvolt = <1000000>;
0153 regulator-max-microvolt = <3000000>;
0154 regulator-always-on;
0155 };
0156
0157 vref_reg: vrefddr {
0158 regulator-name = "V_0V55_VREF_DDR";
0159 regulator-always-on;
0160 };
0161
0162 vgen1_reg: vgen1 {
0163 regulator-name = "V_1V5_CSI";
0164 regulator-min-microvolt = <800000>;
0165 regulator-max-microvolt = <1550000>;
0166 };
0167
0168 vgen2_reg: vgen2 {
0169 regulator-name = "V_0V9_PHY";
0170 regulator-min-microvolt = <850000>;
0171 regulator-max-microvolt = <975000>;
0172 regulator-always-on;
0173 };
0174
0175 vgen3_reg: vgen3 {
0176 regulator-name = "V_1V8_PHY";
0177 regulator-min-microvolt = <1675000>;
0178 regulator-max-microvolt = <1975000>;
0179 regulator-always-on;
0180 };
0181
0182 vgen4_reg: vgen4 {
0183 regulator-name = "V_1V8_VDDA";
0184 regulator-min-microvolt = <1625000>;
0185 regulator-max-microvolt = <1875000>;
0186 regulator-always-on;
0187 };
0188
0189 vgen5_reg: vgen5 {
0190 regulator-name = "V_3V3_PHY";
0191 regulator-min-microvolt = <3075000>;
0192 regulator-max-microvolt = <3625000>;
0193 regulator-always-on;
0194 };
0195
0196 vgen6_reg: vgen6 {
0197 regulator-name = "V_2V8_CAM";
0198 regulator-min-microvolt = <1800000>;
0199 regulator-max-microvolt = <3300000>;
0200 regulator-always-on;
0201 };
0202 };
0203 };
0204
0205 fan-controller@1b {
0206 compatible = "maxim,max6650";
0207 reg = <0x1b>;
0208 maxim,fan-microvolt = <5000000>;
0209 };
0210
0211 rtc@32 {
0212 compatible = "microcrystal,rv8803";
0213 reg = <0x32>;
0214 };
0215
0216 sensor@4b {
0217 compatible = "national,lm75b";
0218 reg = <0x4b>;
0219 };
0220
0221 eeprom@51 {
0222 compatible = "atmel,24c32";
0223 reg = <0x51>;
0224 pagesize = <32>;
0225 };
0226 };
0227
0228 &i2c2 {
0229 clock-frequency = <100000>;
0230 pinctrl-names = "default";
0231 pinctrl-0 = <&pinctrl_i2c2>;
0232 status = "okay";
0233 };
0234
0235 &i2c3 {
0236 clock-frequency = <100000>;
0237 pinctrl-names = "default";
0238 pinctrl-0 = <&pinctrl_i2c3>;
0239 status = "okay";
0240 };
0241
0242 /* M.2 B-key slot */
0243 &pcie0 {
0244 pinctrl-names = "default";
0245 pinctrl-0 = <&pinctrl_pcie0>;
0246 reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
0247 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
0248 <&clk IMX8MQ_CLK_PCIE1_AUX>,
0249 <&clk IMX8MQ_CLK_PCIE1_PHY>,
0250 <&pcie0_refclk>;
0251 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
0252 status = "okay";
0253 };
0254
0255 /* Intel Ethernet Controller I210/I211 */
0256 &pcie1 {
0257 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
0258 <&clk IMX8MQ_CLK_PCIE2_AUX>,
0259 <&clk IMX8MQ_CLK_PCIE2_PHY>,
0260 <&pcie1_refclk>;
0261 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
0262 fsl,max-link-speed = <1>;
0263 status = "okay";
0264 };
0265
0266 &pgc_gpu {
0267 power-supply = <&sw1a_reg>;
0268 };
0269
0270 &pgc_vpu {
0271 power-supply = <&sw1c_reg>;
0272 };
0273
0274 &qspi0 {
0275 pinctrl-names = "default";
0276 pinctrl-0 = <&pinctrl_qspi>;
0277 status = "okay";
0278
0279 flash@0 {
0280 compatible = "jedec,spi-nor";
0281 #address-cells = <1>;
0282 #size-cells = <1>;
0283 reg = <0>;
0284 spi-tx-bus-width = <1>;
0285 spi-rx-bus-width = <4>;
0286 m25p,fast-read;
0287 spi-max-frequency = <50000000>;
0288 };
0289 };
0290
0291 &snvs_pwrkey {
0292 status = "okay";
0293 };
0294
0295 &uart1 {
0296 pinctrl-names = "default";
0297 pinctrl-0 = <&pinctrl_uart1>;
0298 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
0299 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
0300 status = "okay";
0301 };
0302
0303 &uart2 {
0304 pinctrl-names = "default";
0305 pinctrl-0 = <&pinctrl_uart2>;
0306 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
0307 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
0308 status = "okay";
0309 };
0310
0311 &uart3 {
0312 pinctrl-names = "default";
0313 pinctrl-0 = <&pinctrl_uart3>;
0314 uart-has-rtscts;
0315 assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
0316 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
0317 status = "okay";
0318 };
0319
0320 &usb3_phy0 {
0321 status = "okay";
0322 };
0323
0324 &usb3_phy1 {
0325 status = "okay";
0326 };
0327
0328 &usb_dwc3_0 {
0329 pinctrl-names = "default";
0330 pinctrl-0 = <&pinctrl_usb0>;
0331 dr_mode = "otg";
0332 hnp-disable;
0333 srp-disable;
0334 adp-disable;
0335 maximum-speed = "high-speed";
0336 status = "okay";
0337 };
0338
0339 &usb_dwc3_1 {
0340 dr_mode = "host";
0341 status = "okay";
0342 };
0343
0344 &usdhc1 {
0345 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
0346 assigned-clock-rates = <400000000>;
0347 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0348 pinctrl-0 = <&pinctrl_usdhc1>;
0349 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0350 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0351 vqmmc-supply = <&sw4_reg>;
0352 bus-width = <8>;
0353 non-removable;
0354 no-sd;
0355 no-sdio;
0356 status = "okay";
0357 };
0358
0359 &usdhc2 {
0360 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
0361 assigned-clock-rates = <200000000>;
0362 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0363 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0364 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0365 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0366 bus-width = <4>;
0367 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0368 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
0369 vmmc-supply = <®_usdhc2_vmmc>;
0370 status = "okay";
0371 };
0372
0373 &wdog1 {
0374 pinctrl-names = "default";
0375 pinctrl-0 = <&pinctrl_wdog>;
0376 fsl,ext-reset-output;
0377 status = "okay";
0378 };
0379
0380 &iomuxc {
0381 pinctrl-names = "default";
0382 pinctrl-0 = <&pinctrl_hog>;
0383
0384 pinctrl_hog: hoggrp {
0385 fsl,pins = <
0386 MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */
0387 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */
0388 >;
0389 };
0390
0391 pinctrl_gpio: gpiogrp {
0392 fsl,pins = <
0393 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */
0394 MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */
0395 MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */
0396 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */
0397 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */
0398 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */
0399 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */
0400 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */
0401 >;
0402 };
0403
0404 pinctrl_pcie0: pcie0grp {
0405 fsl,pins = <
0406 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */
0407 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */
0408 >;
0409 };
0410
0411 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
0412 fsl,pins = <
0413 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
0414 >;
0415 };
0416
0417 pinctrl_fec1: fec1grp {
0418 fsl,pins = <
0419 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0420 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
0421 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0422 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0423 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0424 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0425 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0426 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0427 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0428 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0429 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0430 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0431 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0432 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0433 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
0434 MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
0435 >;
0436 };
0437
0438 pinctrl_i2c1: i2c1grp {
0439 fsl,pins = <
0440 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
0441 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
0442 >;
0443 };
0444
0445 pinctrl_i2c2: i2c2grp {
0446 fsl,pins = <
0447 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
0448 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
0449 >;
0450 };
0451
0452 pinctrl_i2c3: i2c3grp {
0453 fsl,pins = <
0454 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
0455 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
0456 >;
0457 };
0458
0459 pinctrl_qspi: qspigrp {
0460 fsl,pins = <
0461 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
0462 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0463 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0464 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0465 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0466 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0467 >;
0468 };
0469
0470 pinctrl_ecspi2: ecspi2grp {
0471 fsl,pins = <
0472 MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19
0473 MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19
0474 MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19
0475 >;
0476 };
0477
0478 pinctrl_ecspi2_cs: ecspi2csgrp {
0479 fsl,pins = <
0480 MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
0481 >;
0482 };
0483
0484 pinctrl_uart1: uart1grp {
0485 fsl,pins = <
0486 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
0487 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
0488 >;
0489 };
0490
0491 pinctrl_uart2: uart2grp {
0492 fsl,pins = <
0493 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
0494 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
0495 >;
0496 };
0497
0498 pinctrl_uart3: uart3grp {
0499 fsl,pins = <
0500 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
0501 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
0502 MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
0503 MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
0504 >;
0505 };
0506
0507 pinctrl_usdhc1: usdhc1grp {
0508 fsl,pins = <
0509 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
0510 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
0511 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
0512 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
0513 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
0514 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
0515 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
0516 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
0517 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
0518 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
0519 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
0520 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0521 >;
0522 };
0523
0524 pinctrl_usdhc1_100mhz: usdhc1-100grp {
0525 fsl,pins = <
0526 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
0527 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
0528 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
0529 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
0530 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
0531 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
0532 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
0533 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
0534 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
0535 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
0536 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
0537 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0538 >;
0539 };
0540
0541 pinctrl_usdhc1_200mhz: usdhc1-200grp {
0542 fsl,pins = <
0543 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
0544 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
0545 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
0546 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
0547 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
0548 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
0549 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
0550 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
0551 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
0552 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
0553 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
0554 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0555 >;
0556 };
0557
0558 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0559 fsl,pins = <
0560 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
0561 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19
0562 >;
0563 };
0564
0565 pinctrl_usdhc2: usdhc2grp {
0566 fsl,pins = <
0567 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
0568 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
0569 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
0570 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
0571 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
0572 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
0573 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0574 >;
0575 };
0576
0577 pinctrl_usdhc2_100mhz: usdhc2-100grp {
0578 fsl,pins = <
0579 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
0580 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
0581 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
0582 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
0583 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
0584 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
0585 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0586 >;
0587 };
0588
0589 pinctrl_usdhc2_200mhz: usdhc2-200grp {
0590 fsl,pins = <
0591 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
0592 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
0593 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
0594 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
0595 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
0596 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
0597 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0598 >;
0599 };
0600
0601 pinctrl_usb0: usb0grp {
0602 fsl,pins = <
0603 MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19
0604 MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19
0605 >;
0606 };
0607
0608 pinctrl_wdog: wdoggrp {
0609 fsl,pins = <
0610 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0611 >;
0612 };
0613 };
