0001 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
0002 /*
0003 * Copyright 2017 NXP
0004 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "imx8mq.dtsi"
0010
0011 / {
0012 model = "NXP i.MX8MQ EVK";
0013 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
0014
0015 chosen {
0016 stdout-path = &uart1;
0017 };
0018
0019 memory@40000000 {
0020 device_type = "memory";
0021 reg = <0x00000000 0x40000000 0 0xc0000000>;
0022 };
0023
0024 pcie0_refclk: pcie0-refclk {
0025 compatible = "fixed-clock";
0026 #clock-cells = <0>;
0027 clock-frequency = <100000000>;
0028 };
0029
0030 reg_pcie1: regulator-pcie {
0031 compatible = "regulator-fixed";
0032 pinctrl-names = "default";
0033 pinctrl-0 = <&pinctrl_pcie1_reg>;
0034 regulator-name = "MPCIE_3V3";
0035 regulator-min-microvolt = <3300000>;
0036 regulator-max-microvolt = <3300000>;
0037 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
0038 enable-active-high;
0039 };
0040
0041 reg_usdhc2_vmmc: regulator-vsd-3v3 {
0042 pinctrl-names = "default";
0043 pinctrl-0 = <&pinctrl_reg_usdhc2>;
0044 compatible = "regulator-fixed";
0045 regulator-name = "VSD_3V3";
0046 regulator-min-microvolt = <3300000>;
0047 regulator-max-microvolt = <3300000>;
0048 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0049 enable-active-high;
0050 };
0051
0052 buck2_reg: regulator-buck2 {
0053 pinctrl-names = "default";
0054 pinctrl-0 = <&pinctrl_buck2>;
0055 compatible = "regulator-gpio";
0056 regulator-name = "vdd_arm";
0057 regulator-min-microvolt = <900000>;
0058 regulator-max-microvolt = <1000000>;
0059 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
0060 states = <1000000 0x0
0061 900000 0x1>;
0062 regulator-boot-on;
0063 regulator-always-on;
0064 };
0065
0066 ir-receiver {
0067 compatible = "gpio-ir-receiver";
0068 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
0069 pinctrl-names = "default";
0070 pinctrl-0 = <&pinctrl_ir>;
0071 linux,autosuspend-period = <125>;
0072 };
0073
0074 audio_codec_bt_sco: audio-codec-bt-sco {
0075 compatible = "linux,bt-sco";
0076 #sound-dai-cells = <1>;
0077 };
0078
0079 wm8524: audio-codec {
0080 #sound-dai-cells = <0>;
0081 compatible = "wlf,wm8524";
0082 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
0083 };
0084
0085 sound-bt-sco {
0086 compatible = "simple-audio-card";
0087 simple-audio-card,name = "bt-sco-audio";
0088 simple-audio-card,format = "dsp_a";
0089 simple-audio-card,bitclock-inversion;
0090 simple-audio-card,frame-master = <&btcpu>;
0091 simple-audio-card,bitclock-master = <&btcpu>;
0092
0093 btcpu: simple-audio-card,cpu {
0094 sound-dai = <&sai3>;
0095 dai-tdm-slot-num = <2>;
0096 dai-tdm-slot-width = <16>;
0097 };
0098
0099 simple-audio-card,codec {
0100 sound-dai = <&audio_codec_bt_sco 1>;
0101 };
0102 };
0103
0104 sound-wm8524 {
0105 compatible = "simple-audio-card";
0106 simple-audio-card,name = "wm8524-audio";
0107 simple-audio-card,format = "i2s";
0108 simple-audio-card,frame-master = <&cpudai>;
0109 simple-audio-card,bitclock-master = <&cpudai>;
0110 simple-audio-card,widgets =
0111 "Line", "Left Line Out Jack",
0112 "Line", "Right Line Out Jack";
0113 simple-audio-card,routing =
0114 "Left Line Out Jack", "LINEVOUTL",
0115 "Right Line Out Jack", "LINEVOUTR";
0116
0117 cpudai: simple-audio-card,cpu {
0118 sound-dai = <&sai2>;
0119 };
0120
0121 link_codec: simple-audio-card,codec {
0122 sound-dai = <&wm8524>;
0123 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
0124 };
0125 };
0126
0127 sound-spdif {
0128 compatible = "fsl,imx-audio-spdif";
0129 model = "imx-spdif";
0130 spdif-controller = <&spdif1>;
0131 spdif-out;
0132 spdif-in;
0133 };
0134
0135 sound-hdmi-arc {
0136 compatible = "fsl,imx-audio-spdif";
0137 model = "imx-hdmi-arc";
0138 spdif-controller = <&spdif2>;
0139 spdif-in;
0140 };
0141 };
0142
0143 &A53_0 {
0144 cpu-supply = <&buck2_reg>;
0145 };
0146
0147 &A53_1 {
0148 cpu-supply = <&buck2_reg>;
0149 };
0150
0151 &A53_2 {
0152 cpu-supply = <&buck2_reg>;
0153 };
0154
0155 &A53_3 {
0156 cpu-supply = <&buck2_reg>;
0157 };
0158
0159 &ddrc {
0160 operating-points-v2 = <&ddrc_opp_table>;
0161 status = "okay";
0162
0163 ddrc_opp_table: opp-table {
0164 compatible = "operating-points-v2";
0165
0166 opp-25M {
0167 opp-hz = /bits/ 64 <25000000>;
0168 };
0169
0170 opp-100M {
0171 opp-hz = /bits/ 64 <100000000>;
0172 };
0173
0174 /*
0175 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
0176 */
0177 opp-166M {
0178 opp-hz = /bits/ 64 <166935483>;
0179 };
0180
0181 opp-800M {
0182 opp-hz = /bits/ 64 <800000000>;
0183 };
0184 };
0185 };
0186
0187 &dphy {
0188 status = "okay";
0189 };
0190
0191 &fec1 {
0192 pinctrl-names = "default";
0193 pinctrl-0 = <&pinctrl_fec1>;
0194 phy-mode = "rgmii-id";
0195 phy-handle = <ðphy0>;
0196 fsl,magic-packet;
0197 status = "okay";
0198
0199 mdio {
0200 #address-cells = <1>;
0201 #size-cells = <0>;
0202
0203 ethphy0: ethernet-phy@0 {
0204 compatible = "ethernet-phy-ieee802.3-c22";
0205 reg = <0>;
0206 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
0207 reset-assert-us = <10000>;
0208 qca,disable-smarteee;
0209 vddio-supply = <&vddh>;
0210
0211 vddh: vddh-regulator {
0212 };
0213 };
0214 };
0215 };
0216
0217 &gpio5 {
0218 pinctrl-names = "default";
0219 pinctrl-0 = <&pinctrl_wifi_reset>;
0220
0221 wl-reg-on-hog {
0222 gpio-hog;
0223 gpios = <29 GPIO_ACTIVE_HIGH>;
0224 output-high;
0225 };
0226 };
0227
0228 &i2c1 {
0229 clock-frequency = <100000>;
0230 pinctrl-names = "default";
0231 pinctrl-0 = <&pinctrl_i2c1>;
0232 status = "okay";
0233
0234 pmic@8 {
0235 compatible = "fsl,pfuze100";
0236 reg = <0x8>;
0237
0238 regulators {
0239 sw1a_reg: sw1ab {
0240 regulator-min-microvolt = <825000>;
0241 regulator-max-microvolt = <1100000>;
0242 };
0243
0244 sw1c_reg: sw1c {
0245 regulator-min-microvolt = <825000>;
0246 regulator-max-microvolt = <1100000>;
0247 };
0248
0249 sw2_reg: sw2 {
0250 regulator-min-microvolt = <1100000>;
0251 regulator-max-microvolt = <1100000>;
0252 regulator-always-on;
0253 };
0254
0255 sw3a_reg: sw3ab {
0256 regulator-min-microvolt = <825000>;
0257 regulator-max-microvolt = <1100000>;
0258 regulator-always-on;
0259 };
0260
0261 sw4_reg: sw4 {
0262 regulator-min-microvolt = <1800000>;
0263 regulator-max-microvolt = <1800000>;
0264 regulator-always-on;
0265 };
0266
0267 swbst_reg: swbst {
0268 regulator-min-microvolt = <5000000>;
0269 regulator-max-microvolt = <5150000>;
0270 };
0271
0272 snvs_reg: vsnvs {
0273 regulator-min-microvolt = <1000000>;
0274 regulator-max-microvolt = <3000000>;
0275 regulator-always-on;
0276 };
0277
0278 vref_reg: vrefddr {
0279 regulator-always-on;
0280 };
0281
0282 vgen1_reg: vgen1 {
0283 regulator-min-microvolt = <800000>;
0284 regulator-max-microvolt = <1550000>;
0285 };
0286
0287 vgen2_reg: vgen2 {
0288 regulator-min-microvolt = <850000>;
0289 regulator-max-microvolt = <975000>;
0290 regulator-always-on;
0291 };
0292
0293 vgen3_reg: vgen3 {
0294 regulator-min-microvolt = <1675000>;
0295 regulator-max-microvolt = <1975000>;
0296 regulator-always-on;
0297 };
0298
0299 vgen4_reg: vgen4 {
0300 regulator-min-microvolt = <1625000>;
0301 regulator-max-microvolt = <1875000>;
0302 regulator-always-on;
0303 };
0304
0305 vgen5_reg: vgen5 {
0306 regulator-min-microvolt = <3075000>;
0307 regulator-max-microvolt = <3625000>;
0308 regulator-always-on;
0309 };
0310
0311 vgen6_reg: vgen6 {
0312 regulator-min-microvolt = <1800000>;
0313 regulator-max-microvolt = <3300000>;
0314 };
0315 };
0316 };
0317 };
0318
0319 &lcdif {
0320 status = "okay";
0321 };
0322
0323 &mipi_dsi {
0324 #address-cells = <1>;
0325 #size-cells = <0>;
0326 status = "okay";
0327
0328 panel@0 {
0329 pinctrl-0 = <&pinctrl_mipi_dsi>;
0330 pinctrl-names = "default";
0331 compatible = "raydium,rm67191";
0332 reg = <0>;
0333 reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
0334 dsi-lanes = <4>;
0335
0336 port {
0337 panel_in: endpoint {
0338 remote-endpoint = <&mipi_dsi_out>;
0339 };
0340 };
0341 };
0342
0343 ports {
0344 port@1 {
0345 reg = <1>;
0346 mipi_dsi_out: endpoint {
0347 remote-endpoint = <&panel_in>;
0348 };
0349 };
0350 };
0351 };
0352
0353 &pcie0 {
0354 pinctrl-names = "default";
0355 pinctrl-0 = <&pinctrl_pcie0>;
0356 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
0357 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
0358 <&clk IMX8MQ_CLK_PCIE1_AUX>,
0359 <&clk IMX8MQ_CLK_PCIE1_PHY>,
0360 <&pcie0_refclk>;
0361 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
0362 vph-supply = <&vgen5_reg>;
0363 status = "okay";
0364 };
0365
0366 &pcie1 {
0367 pinctrl-names = "default";
0368 pinctrl-0 = <&pinctrl_pcie1>;
0369 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
0370 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
0371 <&clk IMX8MQ_CLK_PCIE2_AUX>,
0372 <&clk IMX8MQ_CLK_PCIE2_PHY>,
0373 <&pcie0_refclk>;
0374 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
0375 vpcie-supply = <®_pcie1>;
0376 vph-supply = <&vgen5_reg>;
0377 status = "okay";
0378 };
0379
0380 &pgc_gpu {
0381 power-supply = <&sw1a_reg>;
0382 };
0383
0384 &pgc_vpu {
0385 power-supply = <&sw1c_reg>;
0386 };
0387
0388 &qspi0 {
0389 pinctrl-names = "default";
0390 pinctrl-0 = <&pinctrl_qspi>;
0391 status = "okay";
0392
0393 n25q256a: flash@0 {
0394 reg = <0>;
0395 #address-cells = <1>;
0396 #size-cells = <1>;
0397 compatible = "micron,n25q256a", "jedec,spi-nor";
0398 spi-max-frequency = <29000000>;
0399 spi-tx-bus-width = <1>;
0400 spi-rx-bus-width = <4>;
0401 };
0402 };
0403
0404 &sai2 {
0405 pinctrl-names = "default";
0406 pinctrl-0 = <&pinctrl_sai2>;
0407 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
0408 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
0409 assigned-clock-rates = <0>, <24576000>;
0410 status = "okay";
0411 };
0412
0413 &sai3 {
0414 #sound-dai-cells = <0>;
0415 pinctrl-names = "default";
0416 pinctrl-0 = <&pinctrl_sai3>;
0417 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
0418 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
0419 assigned-clock-rates = <24576000>;
0420 status = "okay";
0421 };
0422
0423 &snvs_pwrkey {
0424 status = "okay";
0425 };
0426
0427 &spdif1 {
0428 pinctrl-names = "default";
0429 pinctrl-0 = <&pinctrl_spdif1>;
0430 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
0431 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
0432 assigned-clock-rates = <24576000>;
0433 status = "okay";
0434 };
0435
0436 &spdif2 {
0437 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
0438 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
0439 assigned-clock-rates = <24576000>;
0440 status = "okay";
0441 };
0442
0443 &uart1 {
0444 pinctrl-names = "default";
0445 pinctrl-0 = <&pinctrl_uart1>;
0446 status = "okay";
0447 };
0448
0449 &usb3_phy1 {
0450 status = "okay";
0451 };
0452
0453 &usb_dwc3_1 {
0454 dr_mode = "host";
0455 status = "okay";
0456 };
0457
0458 &usdhc1 {
0459 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
0460 assigned-clock-rates = <400000000>;
0461 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0462 pinctrl-0 = <&pinctrl_usdhc1>;
0463 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0464 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0465 vqmmc-supply = <&sw4_reg>;
0466 bus-width = <8>;
0467 non-removable;
0468 no-sd;
0469 no-sdio;
0470 status = "okay";
0471 };
0472
0473 &usdhc2 {
0474 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
0475 assigned-clock-rates = <200000000>;
0476 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0477 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0478 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0479 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0480 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0481 vmmc-supply = <®_usdhc2_vmmc>;
0482 status = "okay";
0483 };
0484
0485 &wdog1 {
0486 pinctrl-names = "default";
0487 pinctrl-0 = <&pinctrl_wdog>;
0488 fsl,ext-reset-output;
0489 status = "okay";
0490 };
0491
0492 &iomuxc {
0493 pinctrl_buck2: vddarmgrp {
0494 fsl,pins = <
0495 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
0496 >;
0497 };
0498
0499 pinctrl_fec1: fec1grp {
0500 fsl,pins = <
0501 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0502 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
0503 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0504 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0505 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0506 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0507 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0508 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0509 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0510 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0511 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0512 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0513 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0514 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0515 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
0516 >;
0517 };
0518
0519 pinctrl_i2c1: i2c1grp {
0520 fsl,pins = <
0521 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
0522 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
0523 >;
0524 };
0525
0526 pinctrl_ir: irgrp {
0527 fsl,pins = <
0528 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
0529 >;
0530 };
0531
0532 pinctrl_mipi_dsi: mipidsigrp {
0533 fsl,pins = <
0534 MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
0535 >;
0536 };
0537
0538 pinctrl_pcie0: pcie0grp {
0539 fsl,pins = <
0540 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
0541 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
0542 >;
0543 };
0544
0545 pinctrl_pcie1: pcie1grp {
0546 fsl,pins = <
0547 MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
0548 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
0549 >;
0550 };
0551
0552 pinctrl_pcie1_reg: pcie1reggrp {
0553 fsl,pins = <
0554 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
0555 >;
0556 };
0557
0558 pinctrl_qspi: qspigrp {
0559 fsl,pins = <
0560 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
0561 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0562 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0563 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0564 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0565 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0566 >;
0567 };
0568
0569 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
0570 fsl,pins = <
0571 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
0572 >;
0573 };
0574
0575 pinctrl_sai2: sai2grp {
0576 fsl,pins = <
0577 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
0578 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
0579 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
0580 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
0581 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
0582 >;
0583 };
0584
0585 pinctrl_sai3: sai3grp {
0586 fsl,pins = <
0587 MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
0588 MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
0589 MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
0590 MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
0591 >;
0592 };
0593
0594 pinctrl_spdif1: spdif1grp {
0595 fsl,pins = <
0596 MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
0597 MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
0598 >;
0599 };
0600
0601 pinctrl_uart1: uart1grp {
0602 fsl,pins = <
0603 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
0604 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
0605 >;
0606 };
0607
0608 pinctrl_usdhc1: usdhc1grp {
0609 fsl,pins = <
0610 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
0611 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
0612 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
0613 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
0614 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
0615 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
0616 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
0617 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
0618 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
0619 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
0620 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
0621 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0622 >;
0623 };
0624
0625 pinctrl_usdhc1_100mhz: usdhc1-100grp {
0626 fsl,pins = <
0627 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
0628 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
0629 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
0630 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
0631 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
0632 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
0633 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
0634 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
0635 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
0636 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
0637 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
0638 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0639 >;
0640 };
0641
0642 pinctrl_usdhc1_200mhz: usdhc1-200grp {
0643 fsl,pins = <
0644 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
0645 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
0646 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
0647 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
0648 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
0649 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
0650 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
0651 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
0652 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
0653 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
0654 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
0655 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
0656 >;
0657 };
0658
0659 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0660 fsl,pins = <
0661 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
0662 >;
0663 };
0664
0665 pinctrl_usdhc2: usdhc2grp {
0666 fsl,pins = <
0667 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
0668 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
0669 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
0670 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
0671 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
0672 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
0673 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0674 >;
0675 };
0676
0677 pinctrl_usdhc2_100mhz: usdhc2-100grp {
0678 fsl,pins = <
0679 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
0680 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
0681 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
0682 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
0683 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
0684 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
0685 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0686 >;
0687 };
0688
0689 pinctrl_usdhc2_200mhz: usdhc2-200grp {
0690 fsl,pins = <
0691 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
0692 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
0693 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
0694 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
0695 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
0696 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
0697 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
0698 >;
0699 };
0700
0701 pinctrl_wdog: wdog1grp {
0702 fsl,pins = <
0703 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
0704 >;
0705 };
0706
0707 pinctrl_wifi_reset: wifiresetgrp {
0708 fsl,pins = <
0709 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
0710 >;
0711 };
0712 };
