0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2019 NXP
0004 */
0005
0006 #include <dt-bindings/clock/imx8mp-clock.h>
0007 #include <dt-bindings/power/imx8mp-power.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/input.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/thermal/thermal.h>
0012
0013 #include "imx8mp-pinfunc.h"
0014
0015 / {
0016 interrupt-parent = <&gic>;
0017 #address-cells = <2>;
0018 #size-cells = <2>;
0019
0020 aliases {
0021 ethernet0 = &fec;
0022 ethernet1 = &eqos;
0023 gpio0 = &gpio1;
0024 gpio1 = &gpio2;
0025 gpio2 = &gpio3;
0026 gpio3 = &gpio4;
0027 gpio4 = &gpio5;
0028 i2c0 = &i2c1;
0029 i2c1 = &i2c2;
0030 i2c2 = &i2c3;
0031 i2c3 = &i2c4;
0032 i2c4 = &i2c5;
0033 i2c5 = &i2c6;
0034 mmc0 = &usdhc1;
0035 mmc1 = &usdhc2;
0036 mmc2 = &usdhc3;
0037 serial0 = &uart1;
0038 serial1 = &uart2;
0039 serial2 = &uart3;
0040 serial3 = &uart4;
0041 spi0 = &flexspi;
0042 };
0043
0044 cpus {
0045 #address-cells = <1>;
0046 #size-cells = <0>;
0047
0048 A53_0: cpu@0 {
0049 device_type = "cpu";
0050 compatible = "arm,cortex-a53";
0051 reg = <0x0>;
0052 clock-latency = <61036>;
0053 clocks = <&clk IMX8MP_CLK_ARM>;
0054 enable-method = "psci";
0055 i-cache-size = <0x8000>;
0056 i-cache-line-size = <64>;
0057 i-cache-sets = <256>;
0058 d-cache-size = <0x8000>;
0059 d-cache-line-size = <64>;
0060 d-cache-sets = <128>;
0061 next-level-cache = <&A53_L2>;
0062 nvmem-cells = <&cpu_speed_grade>;
0063 nvmem-cell-names = "speed_grade";
0064 operating-points-v2 = <&a53_opp_table>;
0065 #cooling-cells = <2>;
0066 };
0067
0068 A53_1: cpu@1 {
0069 device_type = "cpu";
0070 compatible = "arm,cortex-a53";
0071 reg = <0x1>;
0072 clock-latency = <61036>;
0073 clocks = <&clk IMX8MP_CLK_ARM>;
0074 enable-method = "psci";
0075 i-cache-size = <0x8000>;
0076 i-cache-line-size = <64>;
0077 i-cache-sets = <256>;
0078 d-cache-size = <0x8000>;
0079 d-cache-line-size = <64>;
0080 d-cache-sets = <128>;
0081 next-level-cache = <&A53_L2>;
0082 operating-points-v2 = <&a53_opp_table>;
0083 #cooling-cells = <2>;
0084 };
0085
0086 A53_2: cpu@2 {
0087 device_type = "cpu";
0088 compatible = "arm,cortex-a53";
0089 reg = <0x2>;
0090 clock-latency = <61036>;
0091 clocks = <&clk IMX8MP_CLK_ARM>;
0092 enable-method = "psci";
0093 i-cache-size = <0x8000>;
0094 i-cache-line-size = <64>;
0095 i-cache-sets = <256>;
0096 d-cache-size = <0x8000>;
0097 d-cache-line-size = <64>;
0098 d-cache-sets = <128>;
0099 next-level-cache = <&A53_L2>;
0100 operating-points-v2 = <&a53_opp_table>;
0101 #cooling-cells = <2>;
0102 };
0103
0104 A53_3: cpu@3 {
0105 device_type = "cpu";
0106 compatible = "arm,cortex-a53";
0107 reg = <0x3>;
0108 clock-latency = <61036>;
0109 clocks = <&clk IMX8MP_CLK_ARM>;
0110 enable-method = "psci";
0111 i-cache-size = <0x8000>;
0112 i-cache-line-size = <64>;
0113 i-cache-sets = <256>;
0114 d-cache-size = <0x8000>;
0115 d-cache-line-size = <64>;
0116 d-cache-sets = <128>;
0117 next-level-cache = <&A53_L2>;
0118 operating-points-v2 = <&a53_opp_table>;
0119 #cooling-cells = <2>;
0120 };
0121
0122 A53_L2: l2-cache0 {
0123 compatible = "cache";
0124 cache-level = <2>;
0125 cache-size = <0x80000>;
0126 cache-line-size = <64>;
0127 cache-sets = <512>;
0128 };
0129 };
0130
0131 a53_opp_table: opp-table {
0132 compatible = "operating-points-v2";
0133 opp-shared;
0134
0135 opp-1200000000 {
0136 opp-hz = /bits/ 64 <1200000000>;
0137 opp-microvolt = <850000>;
0138 opp-supported-hw = <0x8a0>, <0x7>;
0139 clock-latency-ns = <150000>;
0140 opp-suspend;
0141 };
0142
0143 opp-1600000000 {
0144 opp-hz = /bits/ 64 <1600000000>;
0145 opp-microvolt = <950000>;
0146 opp-supported-hw = <0xa0>, <0x7>;
0147 clock-latency-ns = <150000>;
0148 opp-suspend;
0149 };
0150
0151 opp-1800000000 {
0152 opp-hz = /bits/ 64 <1800000000>;
0153 opp-microvolt = <1000000>;
0154 opp-supported-hw = <0x20>, <0x3>;
0155 clock-latency-ns = <150000>;
0156 opp-suspend;
0157 };
0158 };
0159
0160 osc_32k: clock-osc-32k {
0161 compatible = "fixed-clock";
0162 #clock-cells = <0>;
0163 clock-frequency = <32768>;
0164 clock-output-names = "osc_32k";
0165 };
0166
0167 osc_24m: clock-osc-24m {
0168 compatible = "fixed-clock";
0169 #clock-cells = <0>;
0170 clock-frequency = <24000000>;
0171 clock-output-names = "osc_24m";
0172 };
0173
0174 clk_ext1: clock-ext1 {
0175 compatible = "fixed-clock";
0176 #clock-cells = <0>;
0177 clock-frequency = <133000000>;
0178 clock-output-names = "clk_ext1";
0179 };
0180
0181 clk_ext2: clock-ext2 {
0182 compatible = "fixed-clock";
0183 #clock-cells = <0>;
0184 clock-frequency = <133000000>;
0185 clock-output-names = "clk_ext2";
0186 };
0187
0188 clk_ext3: clock-ext3 {
0189 compatible = "fixed-clock";
0190 #clock-cells = <0>;
0191 clock-frequency = <133000000>;
0192 clock-output-names = "clk_ext3";
0193 };
0194
0195 clk_ext4: clock-ext4 {
0196 compatible = "fixed-clock";
0197 #clock-cells = <0>;
0198 clock-frequency = <133000000>;
0199 clock-output-names = "clk_ext4";
0200 };
0201
0202 reserved-memory {
0203 #address-cells = <2>;
0204 #size-cells = <2>;
0205 ranges;
0206
0207 dsp_reserved: dsp@92400000 {
0208 reg = <0 0x92400000 0 0x2000000>;
0209 no-map;
0210 };
0211 };
0212
0213 pmu {
0214 compatible = "arm,cortex-a53-pmu";
0215 interrupts = <GIC_PPI 7
0216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0217 };
0218
0219 psci {
0220 compatible = "arm,psci-1.0";
0221 method = "smc";
0222 };
0223
0224 thermal-zones {
0225 cpu-thermal {
0226 polling-delay-passive = <250>;
0227 polling-delay = <2000>;
0228 thermal-sensors = <&tmu 0>;
0229 trips {
0230 cpu_alert0: trip0 {
0231 temperature = <85000>;
0232 hysteresis = <2000>;
0233 type = "passive";
0234 };
0235
0236 cpu_crit0: trip1 {
0237 temperature = <95000>;
0238 hysteresis = <2000>;
0239 type = "critical";
0240 };
0241 };
0242
0243 cooling-maps {
0244 map0 {
0245 trip = <&cpu_alert0>;
0246 cooling-device =
0247 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0248 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0249 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0250 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0251 };
0252 };
0253 };
0254
0255 soc-thermal {
0256 polling-delay-passive = <250>;
0257 polling-delay = <2000>;
0258 thermal-sensors = <&tmu 1>;
0259 trips {
0260 soc_alert0: trip0 {
0261 temperature = <85000>;
0262 hysteresis = <2000>;
0263 type = "passive";
0264 };
0265
0266 soc_crit0: trip1 {
0267 temperature = <95000>;
0268 hysteresis = <2000>;
0269 type = "critical";
0270 };
0271 };
0272
0273 cooling-maps {
0274 map0 {
0275 trip = <&soc_alert0>;
0276 cooling-device =
0277 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0278 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0279 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0280 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0281 };
0282 };
0283 };
0284 };
0285
0286 timer {
0287 compatible = "arm,armv8-timer";
0288 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0289 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0290 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0291 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0292 clock-frequency = <8000000>;
0293 arm,no-tick-in-suspend;
0294 };
0295
0296 soc: soc@0 {
0297 compatible = "fsl,imx8mp-soc", "simple-bus";
0298 #address-cells = <1>;
0299 #size-cells = <1>;
0300 ranges = <0x0 0x0 0x0 0x3e000000>;
0301 nvmem-cells = <&imx8mp_uid>;
0302 nvmem-cell-names = "soc_unique_id";
0303
0304 aips1: bus@30000000 {
0305 compatible = "fsl,aips-bus", "simple-bus";
0306 reg = <0x30000000 0x400000>;
0307 #address-cells = <1>;
0308 #size-cells = <1>;
0309 ranges;
0310
0311 gpio1: gpio@30200000 {
0312 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
0313 reg = <0x30200000 0x10000>;
0314 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
0315 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0316 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
0317 gpio-controller;
0318 #gpio-cells = <2>;
0319 interrupt-controller;
0320 #interrupt-cells = <2>;
0321 gpio-ranges = <&iomuxc 0 5 30>;
0322 };
0323
0324 gpio2: gpio@30210000 {
0325 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
0326 reg = <0x30210000 0x10000>;
0327 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
0328 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0329 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
0330 gpio-controller;
0331 #gpio-cells = <2>;
0332 interrupt-controller;
0333 #interrupt-cells = <2>;
0334 gpio-ranges = <&iomuxc 0 35 21>;
0335 };
0336
0337 gpio3: gpio@30220000 {
0338 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
0339 reg = <0x30220000 0x10000>;
0340 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0341 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0342 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
0343 gpio-controller;
0344 #gpio-cells = <2>;
0345 interrupt-controller;
0346 #interrupt-cells = <2>;
0347 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
0348 };
0349
0350 gpio4: gpio@30230000 {
0351 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
0352 reg = <0x30230000 0x10000>;
0353 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0354 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0355 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
0356 gpio-controller;
0357 #gpio-cells = <2>;
0358 interrupt-controller;
0359 #interrupt-cells = <2>;
0360 gpio-ranges = <&iomuxc 0 82 32>;
0361 };
0362
0363 gpio5: gpio@30240000 {
0364 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
0365 reg = <0x30240000 0x10000>;
0366 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0367 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0368 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
0369 gpio-controller;
0370 #gpio-cells = <2>;
0371 interrupt-controller;
0372 #interrupt-cells = <2>;
0373 gpio-ranges = <&iomuxc 0 114 30>;
0374 };
0375
0376 tmu: tmu@30260000 {
0377 compatible = "fsl,imx8mp-tmu";
0378 reg = <0x30260000 0x10000>;
0379 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
0380 #thermal-sensor-cells = <1>;
0381 };
0382
0383 wdog1: watchdog@30280000 {
0384 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
0385 reg = <0x30280000 0x10000>;
0386 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0387 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
0388 status = "disabled";
0389 };
0390
0391 wdog2: watchdog@30290000 {
0392 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
0393 reg = <0x30290000 0x10000>;
0394 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0395 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
0396 status = "disabled";
0397 };
0398
0399 wdog3: watchdog@302a0000 {
0400 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
0401 reg = <0x302a0000 0x10000>;
0402 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0403 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
0404 status = "disabled";
0405 };
0406
0407 iomuxc: pinctrl@30330000 {
0408 compatible = "fsl,imx8mp-iomuxc";
0409 reg = <0x30330000 0x10000>;
0410 };
0411
0412 gpr: iomuxc-gpr@30340000 {
0413 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
0414 reg = <0x30340000 0x10000>;
0415 };
0416
0417 ocotp: efuse@30350000 {
0418 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
0419 reg = <0x30350000 0x10000>;
0420 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
0421 /* For nvmem subnodes */
0422 #address-cells = <1>;
0423 #size-cells = <1>;
0424
0425 imx8mp_uid: unique-id@420 {
0426 reg = <0x8 0x8>;
0427 };
0428
0429 cpu_speed_grade: speed-grade@10 {
0430 reg = <0x10 4>;
0431 };
0432
0433 eth_mac1: mac-address@90 {
0434 reg = <0x90 6>;
0435 };
0436
0437 eth_mac2: mac-address@96 {
0438 reg = <0x96 6>;
0439 };
0440 };
0441
0442 anatop: anatop@30360000 {
0443 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
0444 "syscon";
0445 reg = <0x30360000 0x10000>;
0446 };
0447
0448 snvs: snvs@30370000 {
0449 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
0450 reg = <0x30370000 0x10000>;
0451
0452 snvs_rtc: snvs-rtc-lp {
0453 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0454 regmap =<&snvs>;
0455 offset = <0x34>;
0456 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0457 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0458 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
0459 clock-names = "snvs-rtc";
0460 };
0461
0462 snvs_pwrkey: snvs-powerkey {
0463 compatible = "fsl,sec-v4.0-pwrkey";
0464 regmap = <&snvs>;
0465 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0466 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
0467 clock-names = "snvs-pwrkey";
0468 linux,keycode = <KEY_POWER>;
0469 wakeup-source;
0470 status = "disabled";
0471 };
0472 };
0473
0474 clk: clock-controller@30380000 {
0475 compatible = "fsl,imx8mp-ccm";
0476 reg = <0x30380000 0x10000>;
0477 #clock-cells = <1>;
0478 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
0479 <&clk_ext3>, <&clk_ext4>;
0480 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
0481 "clk_ext3", "clk_ext4";
0482 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
0483 <&clk IMX8MP_CLK_A53_CORE>,
0484 <&clk IMX8MP_CLK_NOC>,
0485 <&clk IMX8MP_CLK_NOC_IO>,
0486 <&clk IMX8MP_CLK_GIC>,
0487 <&clk IMX8MP_CLK_AUDIO_AHB>,
0488 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
0489 <&clk IMX8MP_AUDIO_PLL1>,
0490 <&clk IMX8MP_AUDIO_PLL2>;
0491 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
0492 <&clk IMX8MP_ARM_PLL_OUT>,
0493 <&clk IMX8MP_SYS_PLL2_1000M>,
0494 <&clk IMX8MP_SYS_PLL1_800M>,
0495 <&clk IMX8MP_SYS_PLL2_500M>,
0496 <&clk IMX8MP_SYS_PLL1_800M>,
0497 <&clk IMX8MP_SYS_PLL1_800M>;
0498 assigned-clock-rates = <0>, <0>,
0499 <1000000000>,
0500 <800000000>,
0501 <500000000>,
0502 <400000000>,
0503 <800000000>,
0504 <393216000>,
0505 <361267200>;
0506 };
0507
0508 src: reset-controller@30390000 {
0509 compatible = "fsl,imx8mp-src", "syscon";
0510 reg = <0x30390000 0x10000>;
0511 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0512 #reset-cells = <1>;
0513 };
0514
0515 gpc: gpc@303a0000 {
0516 compatible = "fsl,imx8mp-gpc";
0517 reg = <0x303a0000 0x1000>;
0518 interrupt-parent = <&gic>;
0519 interrupt-controller;
0520 #interrupt-cells = <3>;
0521
0522 pgc {
0523 #address-cells = <1>;
0524 #size-cells = <0>;
0525
0526 pgc_mipi_phy1: power-domain@0 {
0527 #power-domain-cells = <0>;
0528 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
0529 };
0530
0531 pgc_pcie_phy: power-domain@1 {
0532 #power-domain-cells = <0>;
0533 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
0534 };
0535
0536 pgc_usb1_phy: power-domain@2 {
0537 #power-domain-cells = <0>;
0538 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
0539 };
0540
0541 pgc_usb2_phy: power-domain@3 {
0542 #power-domain-cells = <0>;
0543 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
0544 };
0545
0546 pgc_gpu2d: power-domain@6 {
0547 #power-domain-cells = <0>;
0548 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
0549 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
0550 power-domains = <&pgc_gpumix>;
0551 };
0552
0553 pgc_gpumix: power-domain@7 {
0554 #power-domain-cells = <0>;
0555 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
0556 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
0557 <&clk IMX8MP_CLK_GPU_AHB>;
0558 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
0559 <&clk IMX8MP_CLK_GPU_AHB>;
0560 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
0561 <&clk IMX8MP_SYS_PLL1_800M>;
0562 assigned-clock-rates = <800000000>, <400000000>;
0563 };
0564
0565 pgc_gpu3d: power-domain@9 {
0566 #power-domain-cells = <0>;
0567 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
0568 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
0569 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
0570 power-domains = <&pgc_gpumix>;
0571 };
0572
0573 pgc_mediamix: power-domain@10 {
0574 #power-domain-cells = <0>;
0575 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
0576 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
0577 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
0578 };
0579
0580 pgc_mipi_phy2: power-domain@16 {
0581 #power-domain-cells = <0>;
0582 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
0583 };
0584
0585 pgc_hsiomix: power-domains@17 {
0586 #power-domain-cells = <0>;
0587 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
0588 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
0589 <&clk IMX8MP_CLK_HSIO_ROOT>;
0590 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
0591 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
0592 assigned-clock-rates = <500000000>;
0593 };
0594
0595 pgc_ispdwp: power-domain@18 {
0596 #power-domain-cells = <0>;
0597 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
0598 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
0599 };
0600 };
0601 };
0602 };
0603
0604 aips2: bus@30400000 {
0605 compatible = "fsl,aips-bus", "simple-bus";
0606 reg = <0x30400000 0x400000>;
0607 #address-cells = <1>;
0608 #size-cells = <1>;
0609 ranges;
0610
0611 pwm1: pwm@30660000 {
0612 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
0613 reg = <0x30660000 0x10000>;
0614 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0615 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
0616 <&clk IMX8MP_CLK_PWM1_ROOT>;
0617 clock-names = "ipg", "per";
0618 #pwm-cells = <3>;
0619 status = "disabled";
0620 };
0621
0622 pwm2: pwm@30670000 {
0623 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
0624 reg = <0x30670000 0x10000>;
0625 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0626 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
0627 <&clk IMX8MP_CLK_PWM2_ROOT>;
0628 clock-names = "ipg", "per";
0629 #pwm-cells = <3>;
0630 status = "disabled";
0631 };
0632
0633 pwm3: pwm@30680000 {
0634 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
0635 reg = <0x30680000 0x10000>;
0636 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0637 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
0638 <&clk IMX8MP_CLK_PWM3_ROOT>;
0639 clock-names = "ipg", "per";
0640 #pwm-cells = <3>;
0641 status = "disabled";
0642 };
0643
0644 pwm4: pwm@30690000 {
0645 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
0646 reg = <0x30690000 0x10000>;
0647 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0648 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
0649 <&clk IMX8MP_CLK_PWM4_ROOT>;
0650 clock-names = "ipg", "per";
0651 #pwm-cells = <3>;
0652 status = "disabled";
0653 };
0654
0655 system_counter: timer@306a0000 {
0656 compatible = "nxp,sysctr-timer";
0657 reg = <0x306a0000 0x20000>;
0658 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0659 clocks = <&osc_24m>;
0660 clock-names = "per";
0661 };
0662 };
0663
0664 aips3: bus@30800000 {
0665 compatible = "fsl,aips-bus", "simple-bus";
0666 reg = <0x30800000 0x400000>;
0667 #address-cells = <1>;
0668 #size-cells = <1>;
0669 ranges;
0670
0671 ecspi1: spi@30820000 {
0672 #address-cells = <1>;
0673 #size-cells = <0>;
0674 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
0675 reg = <0x30820000 0x10000>;
0676 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0677 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
0678 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
0679 clock-names = "ipg", "per";
0680 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
0681 dma-names = "rx", "tx";
0682 status = "disabled";
0683 };
0684
0685 ecspi2: spi@30830000 {
0686 #address-cells = <1>;
0687 #size-cells = <0>;
0688 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
0689 reg = <0x30830000 0x10000>;
0690 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0691 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
0692 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
0693 clock-names = "ipg", "per";
0694 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
0695 dma-names = "rx", "tx";
0696 status = "disabled";
0697 };
0698
0699 ecspi3: spi@30840000 {
0700 #address-cells = <1>;
0701 #size-cells = <0>;
0702 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
0703 reg = <0x30840000 0x10000>;
0704 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0705 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
0706 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
0707 clock-names = "ipg", "per";
0708 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
0709 dma-names = "rx", "tx";
0710 status = "disabled";
0711 };
0712
0713 uart1: serial@30860000 {
0714 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
0715 reg = <0x30860000 0x10000>;
0716 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0717 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
0718 <&clk IMX8MP_CLK_UART1_ROOT>;
0719 clock-names = "ipg", "per";
0720 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
0721 dma-names = "rx", "tx";
0722 status = "disabled";
0723 };
0724
0725 uart3: serial@30880000 {
0726 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
0727 reg = <0x30880000 0x10000>;
0728 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0729 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
0730 <&clk IMX8MP_CLK_UART3_ROOT>;
0731 clock-names = "ipg", "per";
0732 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
0733 dma-names = "rx", "tx";
0734 status = "disabled";
0735 };
0736
0737 uart2: serial@30890000 {
0738 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
0739 reg = <0x30890000 0x10000>;
0740 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0741 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
0742 <&clk IMX8MP_CLK_UART2_ROOT>;
0743 clock-names = "ipg", "per";
0744 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
0745 dma-names = "rx", "tx";
0746 status = "disabled";
0747 };
0748
0749 flexcan1: can@308c0000 {
0750 compatible = "fsl,imx8mp-flexcan";
0751 reg = <0x308c0000 0x10000>;
0752 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0753 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
0754 <&clk IMX8MP_CLK_CAN1_ROOT>;
0755 clock-names = "ipg", "per";
0756 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
0757 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
0758 assigned-clock-rates = <40000000>;
0759 fsl,clk-source = /bits/ 8 <0>;
0760 fsl,stop-mode = <&gpr 0x10 4>;
0761 status = "disabled";
0762 };
0763
0764 flexcan2: can@308d0000 {
0765 compatible = "fsl,imx8mp-flexcan";
0766 reg = <0x308d0000 0x10000>;
0767 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0768 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
0769 <&clk IMX8MP_CLK_CAN2_ROOT>;
0770 clock-names = "ipg", "per";
0771 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
0772 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
0773 assigned-clock-rates = <40000000>;
0774 fsl,clk-source = /bits/ 8 <0>;
0775 fsl,stop-mode = <&gpr 0x10 5>;
0776 status = "disabled";
0777 };
0778
0779 crypto: crypto@30900000 {
0780 compatible = "fsl,sec-v4.0";
0781 #address-cells = <1>;
0782 #size-cells = <1>;
0783 reg = <0x30900000 0x40000>;
0784 ranges = <0 0x30900000 0x40000>;
0785 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0786 clocks = <&clk IMX8MP_CLK_AHB>,
0787 <&clk IMX8MP_CLK_IPG_ROOT>;
0788 clock-names = "aclk", "ipg";
0789
0790 sec_jr0: jr@1000 {
0791 compatible = "fsl,sec-v4.0-job-ring";
0792 reg = <0x1000 0x1000>;
0793 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0794 status = "disabled";
0795 };
0796
0797 sec_jr1: jr@2000 {
0798 compatible = "fsl,sec-v4.0-job-ring";
0799 reg = <0x2000 0x1000>;
0800 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0801 };
0802
0803 sec_jr2: jr@3000 {
0804 compatible = "fsl,sec-v4.0-job-ring";
0805 reg = <0x3000 0x1000>;
0806 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0807 };
0808 };
0809
0810 i2c1: i2c@30a20000 {
0811 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
0812 #address-cells = <1>;
0813 #size-cells = <0>;
0814 reg = <0x30a20000 0x10000>;
0815 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0816 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
0817 status = "disabled";
0818 };
0819
0820 i2c2: i2c@30a30000 {
0821 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
0822 #address-cells = <1>;
0823 #size-cells = <0>;
0824 reg = <0x30a30000 0x10000>;
0825 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0826 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
0827 status = "disabled";
0828 };
0829
0830 i2c3: i2c@30a40000 {
0831 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
0832 #address-cells = <1>;
0833 #size-cells = <0>;
0834 reg = <0x30a40000 0x10000>;
0835 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0836 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
0837 status = "disabled";
0838 };
0839
0840 i2c4: i2c@30a50000 {
0841 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
0842 #address-cells = <1>;
0843 #size-cells = <0>;
0844 reg = <0x30a50000 0x10000>;
0845 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0846 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
0847 status = "disabled";
0848 };
0849
0850 uart4: serial@30a60000 {
0851 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
0852 reg = <0x30a60000 0x10000>;
0853 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0854 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
0855 <&clk IMX8MP_CLK_UART4_ROOT>;
0856 clock-names = "ipg", "per";
0857 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
0858 dma-names = "rx", "tx";
0859 status = "disabled";
0860 };
0861
0862 mu: mailbox@30aa0000 {
0863 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
0864 reg = <0x30aa0000 0x10000>;
0865 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0866 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
0867 #mbox-cells = <2>;
0868 };
0869
0870 mu2: mailbox@30e60000 {
0871 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
0872 reg = <0x30e60000 0x10000>;
0873 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
0874 #mbox-cells = <2>;
0875 status = "disabled";
0876 };
0877
0878 i2c5: i2c@30ad0000 {
0879 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
0880 #address-cells = <1>;
0881 #size-cells = <0>;
0882 reg = <0x30ad0000 0x10000>;
0883 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0884 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
0885 status = "disabled";
0886 };
0887
0888 i2c6: i2c@30ae0000 {
0889 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
0890 #address-cells = <1>;
0891 #size-cells = <0>;
0892 reg = <0x30ae0000 0x10000>;
0893 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0894 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
0895 status = "disabled";
0896 };
0897
0898 usdhc1: mmc@30b40000 {
0899 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
0900 reg = <0x30b40000 0x10000>;
0901 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0902 clocks = <&clk IMX8MP_CLK_DUMMY>,
0903 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
0904 <&clk IMX8MP_CLK_USDHC1_ROOT>;
0905 clock-names = "ipg", "ahb", "per";
0906 fsl,tuning-start-tap = <20>;
0907 fsl,tuning-step = <2>;
0908 bus-width = <4>;
0909 status = "disabled";
0910 };
0911
0912 usdhc2: mmc@30b50000 {
0913 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
0914 reg = <0x30b50000 0x10000>;
0915 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0916 clocks = <&clk IMX8MP_CLK_DUMMY>,
0917 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
0918 <&clk IMX8MP_CLK_USDHC2_ROOT>;
0919 clock-names = "ipg", "ahb", "per";
0920 fsl,tuning-start-tap = <20>;
0921 fsl,tuning-step = <2>;
0922 bus-width = <4>;
0923 status = "disabled";
0924 };
0925
0926 usdhc3: mmc@30b60000 {
0927 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
0928 reg = <0x30b60000 0x10000>;
0929 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0930 clocks = <&clk IMX8MP_CLK_DUMMY>,
0931 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
0932 <&clk IMX8MP_CLK_USDHC3_ROOT>;
0933 clock-names = "ipg", "ahb", "per";
0934 fsl,tuning-start-tap = <20>;
0935 fsl,tuning-step = <2>;
0936 bus-width = <4>;
0937 status = "disabled";
0938 };
0939
0940 flexspi: spi@30bb0000 {
0941 compatible = "nxp,imx8mp-fspi";
0942 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
0943 reg-names = "fspi_base", "fspi_mmap";
0944 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0945 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
0946 <&clk IMX8MP_CLK_QSPI_ROOT>;
0947 clock-names = "fspi_en", "fspi";
0948 assigned-clock-rates = <80000000>;
0949 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
0950 #address-cells = <1>;
0951 #size-cells = <0>;
0952 status = "disabled";
0953 };
0954
0955 sdma1: dma-controller@30bd0000 {
0956 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
0957 reg = <0x30bd0000 0x10000>;
0958 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0959 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
0960 <&clk IMX8MP_CLK_AHB>;
0961 clock-names = "ipg", "ahb";
0962 #dma-cells = <3>;
0963 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
0964 };
0965
0966 fec: ethernet@30be0000 {
0967 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
0968 reg = <0x30be0000 0x10000>;
0969 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0970 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0971 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0972 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0973 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
0974 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
0975 <&clk IMX8MP_CLK_ENET_TIMER>,
0976 <&clk IMX8MP_CLK_ENET_REF>,
0977 <&clk IMX8MP_CLK_ENET_PHY_REF>;
0978 clock-names = "ipg", "ahb", "ptp",
0979 "enet_clk_ref", "enet_out";
0980 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
0981 <&clk IMX8MP_CLK_ENET_TIMER>,
0982 <&clk IMX8MP_CLK_ENET_REF>,
0983 <&clk IMX8MP_CLK_ENET_PHY_REF>;
0984 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
0985 <&clk IMX8MP_SYS_PLL2_100M>,
0986 <&clk IMX8MP_SYS_PLL2_125M>,
0987 <&clk IMX8MP_SYS_PLL2_50M>;
0988 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
0989 fsl,num-tx-queues = <3>;
0990 fsl,num-rx-queues = <3>;
0991 nvmem-cells = <ð_mac1>;
0992 nvmem-cell-names = "mac-address";
0993 fsl,stop-mode = <&gpr 0x10 3>;
0994 status = "disabled";
0995 };
0996
0997 eqos: ethernet@30bf0000 {
0998 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
0999 reg = <0x30bf0000 0x10000>;
1000 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1002 interrupt-names = "macirq", "eth_wake_irq";
1003 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1004 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1005 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1006 <&clk IMX8MP_CLK_ENET_QOS>;
1007 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1008 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1009 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1010 <&clk IMX8MP_CLK_ENET_QOS>;
1011 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1012 <&clk IMX8MP_SYS_PLL2_100M>,
1013 <&clk IMX8MP_SYS_PLL2_125M>;
1014 assigned-clock-rates = <0>, <100000000>, <125000000>;
1015 nvmem-cells = <ð_mac2>;
1016 nvmem-cell-names = "mac-address";
1017 intf_mode = <&gpr 0x4>;
1018 status = "disabled";
1019 };
1020 };
1021
1022 noc: interconnect@32700000 {
1023 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1024 reg = <0x32700000 0x100000>;
1025 clocks = <&clk IMX8MP_CLK_NOC>;
1026 #interconnect-cells = <1>;
1027 operating-points-v2 = <&noc_opp_table>;
1028
1029 noc_opp_table: opp-table {
1030 compatible = "operating-points-v2";
1031
1032 opp-200M {
1033 opp-hz = /bits/ 64 <200000000>;
1034 };
1035
1036 opp-1000M {
1037 opp-hz = /bits/ 64 <1000000000>;
1038 };
1039 };
1040 };
1041
1042 aips4: bus@32c00000 {
1043 compatible = "fsl,aips-bus", "simple-bus";
1044 reg = <0x32c00000 0x400000>;
1045 #address-cells = <1>;
1046 #size-cells = <1>;
1047 ranges;
1048
1049 media_blk_ctrl: blk-ctrl@32ec0000 {
1050 compatible = "fsl,imx8mp-media-blk-ctrl",
1051 "syscon";
1052 reg = <0x32ec0000 0x10000>;
1053 power-domains = <&pgc_mediamix>,
1054 <&pgc_mipi_phy1>,
1055 <&pgc_mipi_phy1>,
1056 <&pgc_mediamix>,
1057 <&pgc_mediamix>,
1058 <&pgc_mipi_phy2>,
1059 <&pgc_mediamix>,
1060 <&pgc_ispdwp>,
1061 <&pgc_ispdwp>,
1062 <&pgc_mipi_phy2>;
1063 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1064 "lcdif1", "isi", "mipi-csi2",
1065 "lcdif2", "isp", "dwe",
1066 "mipi-dsi2";
1067 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1068 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1069 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1070 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1071 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1072 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1073 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1074 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1075 clock-names = "apb", "axi", "cam1", "cam2",
1076 "disp1", "disp2", "isp", "phy";
1077
1078 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1079 <&clk IMX8MP_CLK_MEDIA_APB>;
1080 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1081 <&clk IMX8MP_SYS_PLL1_800M>;
1082 assigned-clock-rates = <500000000>, <200000000>;
1083
1084 #power-domain-cells = <1>;
1085 };
1086
1087 hsio_blk_ctrl: blk-ctrl@32f10000 {
1088 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1089 reg = <0x32f10000 0x24>;
1090 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1091 <&clk IMX8MP_CLK_PCIE_ROOT>;
1092 clock-names = "usb", "pcie";
1093 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1094 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1095 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1096 power-domain-names = "bus", "usb", "usb-phy1",
1097 "usb-phy2", "pcie", "pcie-phy";
1098 #power-domain-cells = <1>;
1099 };
1100 };
1101
1102 gpu3d: gpu@38000000 {
1103 compatible = "vivante,gc";
1104 reg = <0x38000000 0x8000>;
1105 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1107 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1108 <&clk IMX8MP_CLK_GPU_ROOT>,
1109 <&clk IMX8MP_CLK_GPU_AHB>;
1110 clock-names = "core", "shader", "bus", "reg";
1111 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1112 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1113 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1114 <&clk IMX8MP_SYS_PLL1_800M>;
1115 assigned-clock-rates = <800000000>, <800000000>;
1116 power-domains = <&pgc_gpu3d>;
1117 };
1118
1119 gpu2d: gpu@38008000 {
1120 compatible = "vivante,gc";
1121 reg = <0x38008000 0x8000>;
1122 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1123 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1124 <&clk IMX8MP_CLK_GPU_ROOT>,
1125 <&clk IMX8MP_CLK_GPU_AHB>;
1126 clock-names = "core", "bus", "reg";
1127 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1128 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1129 assigned-clock-rates = <800000000>;
1130 power-domains = <&pgc_gpu2d>;
1131 };
1132
1133 gic: interrupt-controller@38800000 {
1134 compatible = "arm,gic-v3";
1135 reg = <0x38800000 0x10000>,
1136 <0x38880000 0xc0000>;
1137 #interrupt-cells = <3>;
1138 interrupt-controller;
1139 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1140 interrupt-parent = <&gic>;
1141 };
1142
1143 edacmc: memory-controller@3d400000 {
1144 compatible = "snps,ddrc-3.80a";
1145 reg = <0x3d400000 0x400000>;
1146 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1147 };
1148
1149 ddr-pmu@3d800000 {
1150 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1151 reg = <0x3d800000 0x400000>;
1152 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1153 };
1154
1155 usb3_phy0: usb-phy@381f0040 {
1156 compatible = "fsl,imx8mp-usb-phy";
1157 reg = <0x381f0040 0x40>;
1158 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1159 clock-names = "phy";
1160 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1161 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1162 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
1163 #phy-cells = <0>;
1164 status = "disabled";
1165 };
1166
1167 usb3_0: usb@32f10100 {
1168 compatible = "fsl,imx8mp-dwc3";
1169 reg = <0x32f10100 0x8>,
1170 <0x381f0000 0x20>;
1171 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1172 <&clk IMX8MP_CLK_USB_ROOT>;
1173 clock-names = "hsio", "suspend";
1174 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1175 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1176 #address-cells = <1>;
1177 #size-cells = <1>;
1178 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1179 ranges;
1180 status = "disabled";
1181
1182 usb_dwc3_0: usb@38100000 {
1183 compatible = "snps,dwc3";
1184 reg = <0x38100000 0x10000>;
1185 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1186 <&clk IMX8MP_CLK_USB_CORE_REF>,
1187 <&clk IMX8MP_CLK_USB_ROOT>;
1188 clock-names = "bus_early", "ref", "suspend";
1189 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1190 phys = <&usb3_phy0>, <&usb3_phy0>;
1191 phy-names = "usb2-phy", "usb3-phy";
1192 snps,dis-u2-freeclk-exists-quirk;
1193 };
1194
1195 };
1196
1197 usb3_phy1: usb-phy@382f0040 {
1198 compatible = "fsl,imx8mp-usb-phy";
1199 reg = <0x382f0040 0x40>;
1200 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1201 clock-names = "phy";
1202 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1203 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1204 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
1205 #phy-cells = <0>;
1206 status = "disabled";
1207 };
1208
1209 usb3_1: usb@32f10108 {
1210 compatible = "fsl,imx8mp-dwc3";
1211 reg = <0x32f10108 0x8>,
1212 <0x382f0000 0x20>;
1213 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1214 <&clk IMX8MP_CLK_USB_ROOT>;
1215 clock-names = "hsio", "suspend";
1216 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1217 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1218 #address-cells = <1>;
1219 #size-cells = <1>;
1220 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1221 ranges;
1222 status = "disabled";
1223
1224 usb_dwc3_1: usb@38200000 {
1225 compatible = "snps,dwc3";
1226 reg = <0x38200000 0x10000>;
1227 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1228 <&clk IMX8MP_CLK_USB_CORE_REF>,
1229 <&clk IMX8MP_CLK_USB_ROOT>;
1230 clock-names = "bus_early", "ref", "suspend";
1231 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1232 phys = <&usb3_phy1>, <&usb3_phy1>;
1233 phy-names = "usb2-phy", "usb3-phy";
1234 snps,dis-u2-freeclk-exists-quirk;
1235 };
1236 };
1237
1238 dsp: dsp@3b6e8000 {
1239 compatible = "fsl,imx8mp-dsp";
1240 reg = <0x3b6e8000 0x88000>;
1241 mbox-names = "txdb0", "txdb1",
1242 "rxdb0", "rxdb1";
1243 mboxes = <&mu2 2 0>, <&mu2 2 1>,
1244 <&mu2 3 0>, <&mu2 3 1>;
1245 memory-region = <&dsp_reserved>;
1246 status = "disabled";
1247 };
1248 };
1249 };
