0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright 2022 Toradex
0004 */
0005
0006 #include "dt-bindings/pwm/pwm.h"
0007 #include "imx8mp.dtsi"
0008
0009 / {
0010 chosen {
0011 stdout-path = &uart3;
0012 };
0013
0014 aliases {
0015 /* Ethernet aliases to ensure correct MAC addresses */
0016 ethernet0 = &eqos;
0017 ethernet1 = &fec;
0018 rtc0 = &rtc_i2c;
0019 rtc1 = &snvs_rtc;
0020 };
0021
0022 backlight: backlight {
0023 compatible = "pwm-backlight";
0024 brightness-levels = <0 45 63 88 119 158 203 255>;
0025 default-brightness-level = <4>;
0026 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
0027 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
0028 pinctrl-names = "default";
0029 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
0030 power-supply = <®_3p3v>;
0031 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
0032 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
0033 status = "disabled";
0034 };
0035
0036 backlight_mezzanine: backlight-mezzanine {
0037 compatible = "pwm-backlight";
0038 brightness-levels = <0 45 63 88 119 158 203 255>;
0039 default-brightness-level = <4>;
0040 /* Verdin GPIO 4 (SODIMM 212) */
0041 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
0042 /* Verdin PWM_2 (SODIMM 16) */
0043 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
0044 status = "disabled";
0045 };
0046
0047 gpio-keys {
0048 compatible = "gpio-keys";
0049 pinctrl-names = "default";
0050 pinctrl-0 = <&pinctrl_gpio_keys>;
0051
0052 button-wakeup {
0053 debounce-interval = <10>;
0054 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
0055 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
0056 label = "Wake-Up";
0057 linux,code = <KEY_WAKEUP>;
0058 wakeup-source;
0059 };
0060 };
0061
0062 /* Carrier Board Supplies */
0063 reg_1p8v: regulator-1p8v {
0064 compatible = "regulator-fixed";
0065 regulator-max-microvolt = <1800000>;
0066 regulator-min-microvolt = <1800000>;
0067 regulator-name = "+V1.8_SW";
0068 };
0069
0070 reg_3p3v: regulator-3p3v {
0071 compatible = "regulator-fixed";
0072 regulator-max-microvolt = <3300000>;
0073 regulator-min-microvolt = <3300000>;
0074 regulator-name = "+V3.3_SW";
0075 };
0076
0077 reg_5p0v: regulator-5p0v {
0078 compatible = "regulator-fixed";
0079 regulator-max-microvolt = <5000000>;
0080 regulator-min-microvolt = <5000000>;
0081 regulator-name = "+V5_SW";
0082 };
0083
0084 /* Non PMIC On-module Supplies */
0085 reg_module_eth1phy: regulator-module-eth1phy {
0086 compatible = "regulator-fixed";
0087 enable-active-high;
0088 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
0089 off-on-delay = <500000>;
0090 pinctrl-names = "default";
0091 pinctrl-0 = <&pinctrl_reg_eth>;
0092 regulator-always-on;
0093 regulator-boot-on;
0094 regulator-max-microvolt = <3300000>;
0095 regulator-min-microvolt = <3300000>;
0096 regulator-name = "On-module +V3.3_ETH";
0097 startup-delay-us = <200000>;
0098 vin-supply = <®_vdd_3v3>;
0099 };
0100
0101 reg_usb1_vbus: regulator-usb1-vbus {
0102 compatible = "regulator-fixed";
0103 enable-active-high;
0104 /* Verdin USB_1_EN (SODIMM 155) */
0105 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0106 pinctrl-names = "default";
0107 pinctrl-0 = <&pinctrl_usb1_vbus>;
0108 regulator-max-microvolt = <5000000>;
0109 regulator-min-microvolt = <5000000>;
0110 regulator-name = "USB_1_EN";
0111 };
0112
0113 reg_usb2_vbus: regulator-usb2-vbus {
0114 compatible = "regulator-fixed";
0115 enable-active-high;
0116 /* Verdin USB_2_EN (SODIMM 185) */
0117 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
0118 pinctrl-names = "default";
0119 pinctrl-0 = <&pinctrl_usb2_vbus>;
0120 regulator-max-microvolt = <5000000>;
0121 regulator-min-microvolt = <5000000>;
0122 regulator-name = "USB_2_EN";
0123 };
0124
0125 reg_usdhc2_vmmc: regulator-usdhc2 {
0126 compatible = "regulator-fixed";
0127 enable-active-high;
0128 /* Verdin SD_1_PWR_EN (SODIMM 76) */
0129 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
0130 off-on-delay = <100000>;
0131 pinctrl-names = "default";
0132 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
0133 regulator-max-microvolt = <3300000>;
0134 regulator-min-microvolt = <3300000>;
0135 regulator-name = "+V3.3_SD";
0136 startup-delay-us = <2000>;
0137 };
0138
0139 reserved-memory {
0140 #address-cells = <2>;
0141 #size-cells = <2>;
0142 ranges;
0143
0144 /* Use the kernel configuration settings instead */
0145 /delete-node/ linux,cma;
0146 };
0147 };
0148
0149 &cpu_alert0 {
0150 temperature = <95000>;
0151 };
0152
0153 &cpu_crit0 {
0154 temperature = <105000>;
0155 };
0156
0157 /* Verdin SPI_1 */
0158 &ecspi1 {
0159 #address-cells = <1>;
0160 #size-cells = <0>;
0161 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0162 pinctrl-names = "default";
0163 pinctrl-0 = <&pinctrl_ecspi1>;
0164 };
0165
0166 /* Verdin ETH_1 (On-module PHY) */
0167 &eqos {
0168 phy-handle = <ðphy0>;
0169 phy-mode = "rgmii-id";
0170 phy-supply = <®_module_eth1phy>;
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&pinctrl_eqos>;
0173 snps,force_thresh_dma_mode;
0174 snps,mtl-rx-config = <&mtl_rx_setup>;
0175 snps,mtl-tx-config = <&mtl_tx_setup>;
0176
0177 mdio {
0178 compatible = "snps,dwmac-mdio";
0179 #address-cells = <1>;
0180 #size-cells = <0>;
0181
0182 ethphy0: ethernet-phy@7 {
0183 compatible = "ethernet-phy-ieee802.3-c22";
0184 eee-broken-100tx;
0185 eee-broken-1000t;
0186 interrupt-parent = <&gpio1>;
0187 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
0188 micrel,led-mode = <0>;
0189 reg = <7>;
0190 };
0191 };
0192
0193 mtl_rx_setup: rx-queues-config {
0194 snps,rx-queues-to-use = <5>;
0195 snps,rx-sched-sp;
0196
0197 queue0 {
0198 snps,dcb-algorithm;
0199 snps,priority = <0x1>;
0200 snps,map-to-dma-channel = <0>;
0201 };
0202
0203 queue1 {
0204 snps,dcb-algorithm;
0205 snps,priority = <0x2>;
0206 snps,map-to-dma-channel = <1>;
0207 };
0208
0209 queue2 {
0210 snps,dcb-algorithm;
0211 snps,priority = <0x4>;
0212 snps,map-to-dma-channel = <2>;
0213 };
0214
0215 queue3 {
0216 snps,dcb-algorithm;
0217 snps,priority = <0x8>;
0218 snps,map-to-dma-channel = <3>;
0219 };
0220
0221 queue4 {
0222 snps,dcb-algorithm;
0223 snps,priority = <0xf0>;
0224 snps,map-to-dma-channel = <4>;
0225 };
0226 };
0227
0228 mtl_tx_setup: tx-queues-config {
0229 snps,tx-queues-to-use = <5>;
0230 snps,tx-sched-sp;
0231
0232 queue0 {
0233 snps,dcb-algorithm;
0234 snps,priority = <0x1>;
0235 };
0236
0237 queue1 {
0238 snps,dcb-algorithm;
0239 snps,priority = <0x2>;
0240 };
0241
0242 queue2 {
0243 snps,dcb-algorithm;
0244 snps,priority = <0x4>;
0245 };
0246
0247 queue3 {
0248 snps,dcb-algorithm;
0249 snps,priority = <0x8>;
0250 };
0251
0252 queue4 {
0253 snps,dcb-algorithm;
0254 snps,priority = <0xf0>;
0255 };
0256 };
0257 };
0258
0259 /* Verdin ETH_2_RGMII */
0260 &fec {
0261 fsl,magic-packet;
0262 phy-handle = <ðphy1>;
0263 phy-mode = "rgmii-id";
0264 pinctrl-names = "default", "sleep";
0265 pinctrl-0 = <&pinctrl_fec>;
0266 pinctrl-1 = <&pinctrl_fec_sleep>;
0267
0268 mdio {
0269 #address-cells = <1>;
0270 #size-cells = <0>;
0271
0272 ethphy1: ethernet-phy@7 {
0273 compatible = "ethernet-phy-ieee802.3-c22";
0274 interrupt-parent = <&gpio4>;
0275 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
0276 micrel,led-mode = <0>;
0277 reg = <7>;
0278 };
0279 };
0280 };
0281
0282 /* Verdin CAN_1 */
0283 &flexcan1 {
0284 pinctrl-names = "default";
0285 pinctrl-0 = <&pinctrl_flexcan1>;
0286 status = "disabled";
0287 };
0288
0289
0290 /* Verdin CAN_2 */
0291 &flexcan2 {
0292 pinctrl-names = "default";
0293 pinctrl-0 = <&pinctrl_flexcan2>;
0294 status = "disabled";
0295 };
0296
0297 /* Verdin QSPI_1 */
0298 &flexspi {
0299 pinctrl-names = "default";
0300 pinctrl-0 = <&pinctrl_flexspi0>;
0301 };
0302
0303 &gpio1 {
0304 gpio-line-names = "SODIMM_206",
0305 "SODIMM_208",
0306 "",
0307 "",
0308 "",
0309 "SODIMM_210",
0310 "SODIMM_212",
0311 "SODIMM_216",
0312 "SODIMM_218",
0313 "",
0314 "",
0315 "SODIMM_16",
0316 "SODIMM_155",
0317 "SODIMM_157",
0318 "SODIMM_185",
0319 "SODIMM_91";
0320 };
0321
0322 &gpio2 {
0323 gpio-line-names = "",
0324 "",
0325 "",
0326 "",
0327 "",
0328 "",
0329 "SODIMM_143",
0330 "SODIMM_141",
0331 "",
0332 "",
0333 "SODIMM_161",
0334 "",
0335 "SODIMM_84",
0336 "SODIMM_78",
0337 "SODIMM_74",
0338 "SODIMM_80",
0339 "SODIMM_82",
0340 "SODIMM_70",
0341 "SODIMM_72";
0342
0343 ctrl-sleep-moci-hog {
0344 gpio-hog;
0345 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
0346 gpios = <29 GPIO_ACTIVE_HIGH>;
0347 line-name = "CTRL_SLEEP_MOCI#";
0348 output-high;
0349 pinctrl-names = "default";
0350 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
0351 };
0352 };
0353
0354 &gpio3 {
0355 gpio-line-names = "SODIMM_52",
0356 "SODIMM_54",
0357 "",
0358 "",
0359 "",
0360 "",
0361 "SODIMM_56",
0362 "SODIMM_58",
0363 "SODIMM_60",
0364 "SODIMM_62",
0365 "",
0366 "",
0367 "",
0368 "",
0369 "SODIMM_66",
0370 "",
0371 "SODIMM_64",
0372 "",
0373 "",
0374 "SODIMM_34",
0375 "SODIMM_19",
0376 "",
0377 "SODIMM_32",
0378 "",
0379 "",
0380 "SODIMM_30",
0381 "SODIMM_59",
0382 "SODIMM_57",
0383 "SODIMM_63",
0384 "SODIMM_61";
0385 };
0386
0387 &gpio4 {
0388 gpio-line-names = "SODIMM_252",
0389 "SODIMM_222",
0390 "SODIMM_36",
0391 "SODIMM_220",
0392 "SODIMM_193",
0393 "SODIMM_191",
0394 "SODIMM_201",
0395 "SODIMM_203",
0396 "SODIMM_205",
0397 "SODIMM_207",
0398 "SODIMM_199",
0399 "SODIMM_197",
0400 "SODIMM_221",
0401 "SODIMM_219",
0402 "SODIMM_217",
0403 "SODIMM_215",
0404 "SODIMM_211",
0405 "SODIMM_213",
0406 "SODIMM_189",
0407 "SODIMM_244",
0408 "SODIMM_38",
0409 "",
0410 "SODIMM_76",
0411 "SODIMM_135",
0412 "SODIMM_133",
0413 "SODIMM_17",
0414 "SODIMM_24",
0415 "SODIMM_26",
0416 "SODIMM_21",
0417 "SODIMM_256",
0418 "SODIMM_48",
0419 "SODIMM_44";
0420 };
0421
0422 /* On-module I2C */
0423 &i2c1 {
0424 clock-frequency = <400000>;
0425 pinctrl-names = "default", "gpio";
0426 pinctrl-0 = <&pinctrl_i2c1>;
0427 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0428 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0429 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0430 status = "okay";
0431
0432 pca9450: pmic@25 {
0433 compatible = "nxp,pca9450c";
0434 interrupt-parent = <&gpio1>;
0435 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
0436 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0437 pinctrl-names = "default";
0438 pinctrl-0 = <&pinctrl_pmic>;
0439 reg = <0x25>;
0440 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
0441
0442 /*
0443 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
0444 * I2C level shifter for the TLA2024 ADC behind this PMIC.
0445 */
0446
0447 regulators {
0448 BUCK1 {
0449 regulator-always-on;
0450 regulator-boot-on;
0451 regulator-max-microvolt = <1000000>;
0452 regulator-min-microvolt = <720000>;
0453 regulator-name = "On-module +VDD_SOC (BUCK1)";
0454 regulator-ramp-delay = <3125>;
0455 };
0456
0457 BUCK2 {
0458 nxp,dvs-run-voltage = <950000>;
0459 nxp,dvs-standby-voltage = <850000>;
0460 regulator-always-on;
0461 regulator-boot-on;
0462 regulator-max-microvolt = <1025000>;
0463 regulator-min-microvolt = <720000>;
0464 regulator-name = "On-module +VDD_ARM (BUCK2)";
0465 regulator-ramp-delay = <3125>;
0466 };
0467
0468 reg_vdd_3v3: BUCK4 {
0469 regulator-always-on;
0470 regulator-boot-on;
0471 regulator-max-microvolt = <3300000>;
0472 regulator-min-microvolt = <3300000>;
0473 regulator-name = "On-module +V3.3 (BUCK4)";
0474 };
0475
0476 reg_vdd_1v8: BUCK5 {
0477 regulator-always-on;
0478 regulator-boot-on;
0479 regulator-max-microvolt = <1800000>;
0480 regulator-min-microvolt = <1800000>;
0481 regulator-name = "PWR_1V8_MOCI (BUCK5)";
0482 };
0483
0484 BUCK6 {
0485 regulator-always-on;
0486 regulator-boot-on;
0487 regulator-max-microvolt = <1155000>;
0488 regulator-min-microvolt = <1045000>;
0489 regulator-name = "On-module +VDD_DDR (BUCK6)";
0490 };
0491
0492 LDO1 {
0493 regulator-always-on;
0494 regulator-boot-on;
0495 regulator-max-microvolt = <1950000>;
0496 regulator-min-microvolt = <1650000>;
0497 regulator-name = "On-module +V1.8_SNVS (LDO1)";
0498 };
0499
0500 LDO2 {
0501 regulator-always-on;
0502 regulator-boot-on;
0503 regulator-max-microvolt = <1150000>;
0504 regulator-min-microvolt = <800000>;
0505 regulator-name = "On-module +V0.8_SNVS (LDO2)";
0506 };
0507
0508 LDO3 {
0509 regulator-always-on;
0510 regulator-boot-on;
0511 regulator-max-microvolt = <1800000>;
0512 regulator-min-microvolt = <1800000>;
0513 regulator-name = "On-module +V1.8A (LDO3)";
0514 };
0515
0516 LDO4 {
0517 regulator-always-on;
0518 regulator-boot-on;
0519 regulator-max-microvolt = <3300000>;
0520 regulator-min-microvolt = <3300000>;
0521 regulator-name = "On-module +V3.3_ADC (LDO4)";
0522 };
0523
0524 LDO5 {
0525 regulator-max-microvolt = <3300000>;
0526 regulator-min-microvolt = <1800000>;
0527 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
0528 };
0529 };
0530 };
0531
0532 rtc_i2c: rtc@32 {
0533 compatible = "epson,rx8130";
0534 reg = <0x32>;
0535 };
0536
0537 /* On-module temperature sensor */
0538 hwmon_temp_module: sensor@48 {
0539 compatible = "ti,tmp1075";
0540 reg = <0x48>;
0541 vs-supply = <®_vdd_1v8>;
0542 };
0543
0544 adc@49 {
0545 compatible = "ti,ads1015";
0546 reg = <0x49>;
0547 #address-cells = <1>;
0548 #size-cells = <0>;
0549
0550 /* Verdin I2C_1 (ADC_4 - ADC_3) */
0551 channel@0 {
0552 reg = <0>;
0553 ti,datarate = <4>;
0554 ti,gain = <2>;
0555 };
0556
0557 /* Verdin I2C_1 (ADC_4 - ADC_1) */
0558 channel@1 {
0559 reg = <1>;
0560 ti,datarate = <4>;
0561 ti,gain = <2>;
0562 };
0563
0564 /* Verdin I2C_1 (ADC_3 - ADC_1) */
0565 channel@2 {
0566 reg = <2>;
0567 ti,datarate = <4>;
0568 ti,gain = <2>;
0569 };
0570
0571 /* Verdin I2C_1 (ADC_2 - ADC_1) */
0572 channel@3 {
0573 reg = <3>;
0574 ti,datarate = <4>;
0575 ti,gain = <2>;
0576 };
0577
0578 /* Verdin I2C_1 ADC_4 */
0579 channel@4 {
0580 reg = <4>;
0581 ti,datarate = <4>;
0582 ti,gain = <2>;
0583 };
0584
0585 /* Verdin I2C_1 ADC_3 */
0586 channel@5 {
0587 reg = <5>;
0588 ti,datarate = <4>;
0589 ti,gain = <2>;
0590 };
0591
0592 /* Verdin I2C_1 ADC_2 */
0593 channel@6 {
0594 reg = <6>;
0595 ti,datarate = <4>;
0596 ti,gain = <2>;
0597 };
0598
0599 /* Verdin I2C_1 ADC_1 */
0600 channel@7 {
0601 reg = <7>;
0602 ti,datarate = <4>;
0603 ti,gain = <2>;
0604 };
0605 };
0606
0607 eeprom@50 {
0608 compatible = "st,24c02";
0609 pagesize = <16>;
0610 reg = <0x50>;
0611 };
0612 };
0613
0614 /* Verdin I2C_2_DSI */
0615 &i2c2 {
0616 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
0617 clock-frequency = <10000>;
0618 pinctrl-names = "default", "gpio";
0619 pinctrl-0 = <&pinctrl_i2c2>;
0620 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0621 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0622 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0623
0624 atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
0625 compatible = "atmel,maxtouch";
0626 /* Verdin GPIO_3 (SODIMM 210) */
0627 interrupt-parent = <&gpio1>;
0628 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
0629 reg = <0x4a>;
0630 /* Verdin GPIO_2 (SODIMM 208) */
0631 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
0632 status = "disabled";
0633 };
0634 };
0635
0636 /* TODO: Verdin I2C_3_HDMI */
0637
0638 /* Verdin I2C_4_CSI */
0639 &i2c3 {
0640 clock-frequency = <400000>;
0641 pinctrl-names = "default", "gpio";
0642 pinctrl-0 = <&pinctrl_i2c3>;
0643 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0644 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0645 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0646 };
0647
0648 /* Verdin I2C_1 */
0649 &i2c4 {
0650 clock-frequency = <400000>;
0651 pinctrl-names = "default", "gpio";
0652 pinctrl-0 = <&pinctrl_i2c4>;
0653 pinctrl-1 = <&pinctrl_i2c4_gpio>;
0654 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0655 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0656
0657 gpio_expander_21: gpio-expander@21 {
0658 compatible = "nxp,pcal6416";
0659 #gpio-cells = <2>;
0660 gpio-controller;
0661 reg = <0x21>;
0662 vcc-supply = <®_3p3v>;
0663 status = "disabled";
0664 };
0665
0666 lvds_ti_sn65dsi83: bridge@2c {
0667 compatible = "ti,sn65dsi83";
0668 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
0669 /* Verdin GPIO_10_DSI (SODIMM 21) */
0670 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
0671 pinctrl-names = "default";
0672 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
0673 reg = <0x2c>;
0674 status = "disabled";
0675 };
0676
0677 /* Current measurement into module VCC */
0678 hwmon: hwmon@40 {
0679 compatible = "ti,ina219";
0680 reg = <0x40>;
0681 shunt-resistor = <10000>;
0682 status = "disabled";
0683 };
0684
0685 hdmi_lontium_lt8912: hdmi@48 {
0686 compatible = "lontium,lt8912b";
0687 pinctrl-names = "default";
0688 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
0689 reg = <0x48>;
0690 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
0691 /* Verdin GPIO_10_DSI (SODIMM 21) */
0692 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
0693 status = "disabled";
0694 };
0695
0696 atmel_mxt_ts: touch@4a {
0697 compatible = "atmel,maxtouch";
0698 /*
0699 * Verdin GPIO_9_DSI
0700 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
0701 */
0702 interrupt-parent = <&gpio4>;
0703 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
0704 pinctrl-names = "default";
0705 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
0706 reg = <0x4a>;
0707 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
0708 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
0709 status = "disabled";
0710 };
0711
0712 /* Temperature sensor on carrier board */
0713 hwmon_temp: sensor@4f {
0714 compatible = "ti,tmp75c";
0715 reg = <0x4f>;
0716 status = "disabled";
0717 };
0718
0719 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
0720 eeprom_display_adapter: eeprom@50 {
0721 compatible = "st,24c02";
0722 pagesize = <16>;
0723 reg = <0x50>;
0724 status = "disabled";
0725 };
0726
0727 /* EEPROM on carrier board */
0728 eeprom_carrier_board: eeprom@57 {
0729 compatible = "st,24c02";
0730 pagesize = <16>;
0731 reg = <0x57>;
0732 status = "disabled";
0733 };
0734 };
0735
0736 /* TODO: Verdin PCIE_1 */
0737
0738 /* Verdin PWM_1 */
0739 &pwm1 {
0740 pinctrl-names = "default";
0741 pinctrl-0 = <&pinctrl_pwm_1>;
0742 #pwm-cells = <3>;
0743 };
0744
0745 /* Verdin PWM_2 */
0746 &pwm2 {
0747 pinctrl-names = "default";
0748 pinctrl-0 = <&pinctrl_pwm_2>;
0749 #pwm-cells = <3>;
0750 };
0751
0752 /* Verdin PWM_3_DSI */
0753 &pwm3 {
0754 pinctrl-names = "default";
0755 pinctrl-0 = <&pinctrl_pwm_3>;
0756 #pwm-cells = <3>;
0757 };
0758
0759 /* TODO: Verdin I2S_1 */
0760
0761 /* TODO: Verdin I2S_2 */
0762
0763 &snvs_pwrkey {
0764 status = "okay";
0765 };
0766
0767 /* Verdin UART_1 */
0768 &uart1 {
0769 pinctrl-names = "default";
0770 pinctrl-0 = <&pinctrl_uart1>;
0771 uart-has-rtscts;
0772 };
0773
0774 /* Verdin UART_2 */
0775 &uart2 {
0776 pinctrl-names = "default";
0777 pinctrl-0 = <&pinctrl_uart2>;
0778 uart-has-rtscts;
0779 };
0780
0781 /* Verdin UART_3, used as the Linux Console */
0782 &uart3 {
0783 pinctrl-names = "default";
0784 pinctrl-0 = <&pinctrl_uart3>;
0785 };
0786
0787 /* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
0788 &uart4 {
0789 pinctrl-names = "default";
0790 pinctrl-0 = <&pinctrl_uart4>;
0791 };
0792
0793 /* Verdin USB_1 */
0794 &usb3_phy0 {
0795 vbus-supply = <®_usb1_vbus>;
0796 };
0797
0798 &usb_dwc3_0 {
0799 adp-disable;
0800 dr_mode = "otg";
0801 hnp-disable;
0802 maximum-speed = "high-speed";
0803 over-current-active-low;
0804 pinctrl-names = "default";
0805 pinctrl-0 = <&pinctrl_usb_1_id>;
0806 srp-disable;
0807 };
0808
0809 /* Verdin USB_2 */
0810 &usb3_phy1 {
0811 vbus-supply = <®_usb2_vbus>;
0812 };
0813
0814 &usb_dwc3_1 {
0815 disable-over-current;
0816 dr_mode = "host";
0817 };
0818
0819 /* Verdin SD_1 */
0820 &usdhc2 {
0821 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
0822 assigned-clock-rates = <400000000>;
0823 bus-width = <4>;
0824 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0825 disable-wp;
0826 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
0827 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
0828 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
0829 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
0830 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
0831 vmmc-supply = <®_usdhc2_vmmc>;
0832 };
0833
0834 /* On-module eMMC */
0835 &usdhc3 {
0836 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
0837 assigned-clock-rates = <400000000>;
0838 bus-width = <8>;
0839 non-removable;
0840 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0841 pinctrl-0 = <&pinctrl_usdhc3>;
0842 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0843 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0844 status = "okay";
0845 };
0846
0847 &wdog1 {
0848 fsl,ext-reset-output;
0849 pinctrl-names = "default";
0850 pinctrl-0 = <&pinctrl_wdog>;
0851 status = "okay";
0852 };
0853
0854 &iomuxc {
0855 pinctrl_bt_uart: btuartgrp {
0856 fsl,pins =
0857 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>,
0858 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>,
0859 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>,
0860 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>;
0861 };
0862
0863 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
0864 fsl,pins =
0865 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */
0866 };
0867
0868 pinctrl_ecspi1: ecspi1grp {
0869 fsl,pins =
0870 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */
0871 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */
0872 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */
0873 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */
0874 };
0875
0876 /* Connection On Board PHY */
0877 pinctrl_eqos: eqosgrp {
0878 fsl,pins =
0879 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
0880 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
0881 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
0882 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
0883 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
0884 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
0885 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
0886 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
0887 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
0888 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
0889 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
0890 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
0891 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
0892 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
0893 };
0894
0895 /* ETH_INT# shared with TPM_INT# (usually N/A) */
0896 pinctrl_eth_tpm_int: ethtpmintgrp {
0897 fsl,pins =
0898 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>;
0899 };
0900
0901 /* Connection Carrier Board PHY ETH_2 */
0902 pinctrl_fec: fecgrp {
0903 fsl,pins =
0904 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
0905 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
0906 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
0907 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
0908 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
0909 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
0910 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
0911 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
0912 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */
0913 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */
0914 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */
0915 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */
0916 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */
0917 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */
0918 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */
0919 };
0920
0921 pinctrl_fec_sleep: fecsleepgrp {
0922 fsl,pins =
0923 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
0924 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
0925 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
0926 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
0927 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
0928 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
0929 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
0930 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
0931 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */
0932 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */
0933 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */
0934 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */
0935 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */
0936 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */
0937 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */
0938 };
0939
0940 pinctrl_flexcan1: flexcan1grp {
0941 fsl,pins =
0942 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */
0943 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */
0944 };
0945
0946 pinctrl_flexcan2: flexcan2grp {
0947 fsl,pins =
0948 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */
0949 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */
0950 };
0951
0952 pinctrl_flexspi0: flexspi0grp {
0953 fsl,pins =
0954 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
0955 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */
0956 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */
0957 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */
0958 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */
0959 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */
0960 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */
0961 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
0962 };
0963
0964 pinctrl_gpio1: gpio1grp {
0965 fsl,pins =
0966 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */
0967 };
0968
0969 pinctrl_gpio2: gpio2grp {
0970 fsl,pins =
0971 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */
0972 };
0973
0974 pinctrl_gpio3: gpio3grp {
0975 fsl,pins =
0976 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */
0977 };
0978
0979 pinctrl_gpio4: gpio4grp {
0980 fsl,pins =
0981 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */
0982 };
0983
0984 pinctrl_gpio5: gpio5grp {
0985 fsl,pins =
0986 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */
0987 };
0988
0989 pinctrl_gpio6: gpio6grp {
0990 fsl,pins =
0991 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */
0992 };
0993
0994 pinctrl_gpio7: gpio7grp {
0995 fsl,pins =
0996 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */
0997 };
0998
0999 pinctrl_gpio8: gpio8grp {
1000 fsl,pins =
1001 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */
1002 };
1003
1004 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
1005 pinctrl_gpio_9_dsi: gpio9dsigrp {
1006 fsl,pins =
1007 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */
1008 };
1009
1010 /* Verdin GPIO_10_DSI */
1011 pinctrl_gpio_10_dsi: gpio10dsigrp {
1012 fsl,pins =
1013 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */
1014 };
1015
1016 /* Non-wifi MSP usage only */
1017 pinctrl_gpio_hog1: gpiohog1grp {
1018 fsl,pins =
1019 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */
1020 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */
1021 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */
1022 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */
1023 };
1024
1025 /* USB_2_OC# */
1026 pinctrl_gpio_hog2: gpiohog2grp {
1027 fsl,pins =
1028 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */
1029 };
1030
1031 pinctrl_gpio_hog3: gpiohog3grp {
1032 fsl,pins =
1033 <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */
1034 /* CSI_1_MCLK */
1035 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
1036 };
1037
1038 /* Wifi usage only */
1039 pinctrl_gpio_hog4: gpiohog4grp {
1040 fsl,pins =
1041 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */
1042 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */
1043 };
1044
1045 pinctrl_gpio_keys: gpiokeysgrp {
1046 fsl,pins =
1047 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */
1048 };
1049
1050 pinctrl_hdmi_hog: hdmihoggrp {
1051 fsl,pins =
1052 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
1053 <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */
1054 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */
1055 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
1056 };
1057
1058 /* On-module I2C */
1059 pinctrl_i2c1: i2c1grp {
1060 fsl,pins =
1061 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
1062 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
1063 };
1064
1065 pinctrl_i2c1_gpio: i2c1gpiogrp {
1066 fsl,pins =
1067 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
1068 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
1069 };
1070
1071 /* Verdin I2C_2_DSI */
1072 pinctrl_i2c2: i2c2grp {
1073 fsl,pins =
1074 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */
1075 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */
1076 };
1077
1078 pinctrl_i2c2_gpio: i2c2gpiogrp {
1079 fsl,pins =
1080 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
1081 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
1082 };
1083
1084 /* Verdin I2C_4_CSI */
1085 pinctrl_i2c3: i2c3grp {
1086 fsl,pins =
1087 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */
1088 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */
1089 };
1090
1091 pinctrl_i2c3_gpio: i2c3gpiogrp {
1092 fsl,pins =
1093 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
1094 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
1095 };
1096
1097 /* Verdin I2C_1 */
1098 pinctrl_i2c4: i2c4grp {
1099 fsl,pins =
1100 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */
1101 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */
1102 };
1103
1104 pinctrl_i2c4_gpio: i2c4gpiogrp {
1105 fsl,pins =
1106 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
1107 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
1108 };
1109
1110 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1111 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1112 fsl,pins =
1113 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */
1114 };
1115
1116 /* Verdin I2S_2_D_OUT shared with SAI3 */
1117 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1118 fsl,pins =
1119 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */
1120 };
1121
1122 pinctrl_pcie: pciegrp {
1123 fsl,pins =
1124 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */
1125 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
1126 };
1127
1128 pinctrl_pmic: pmicirqgrp {
1129 fsl,pins =
1130 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
1131 };
1132
1133 pinctrl_pwm_1: pwm1grp {
1134 fsl,pins =
1135 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */
1136 };
1137
1138 pinctrl_pwm_2: pwm2grp {
1139 fsl,pins =
1140 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */
1141 };
1142
1143 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1144 pinctrl_pwm_3: pwm3grp {
1145 fsl,pins =
1146 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */
1147 };
1148
1149 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1150 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1151 fsl,pins =
1152 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */
1153 };
1154
1155 pinctrl_reg_eth: regethgrp {
1156 fsl,pins =
1157 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
1158 };
1159
1160 pinctrl_sai1: sai1grp {
1161 fsl,pins =
1162 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */
1163 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */
1164 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */
1165 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */
1166 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */
1167 };
1168
1169 pinctrl_sai3: sai3grp {
1170 fsl,pins =
1171 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
1172 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */
1173 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */
1174 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */
1175 };
1176
1177 pinctrl_uart1: uart1grp {
1178 fsl,pins =
1179 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */
1180 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */
1181 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */
1182 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */
1183 };
1184
1185 pinctrl_uart2: uart2grp {
1186 fsl,pins =
1187 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */
1188 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */
1189 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */
1190 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */
1191 };
1192
1193 pinctrl_uart3: uart3grp {
1194 fsl,pins =
1195 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */
1196 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */
1197 };
1198
1199 /* Non-wifi usage only */
1200 pinctrl_uart4: uart4grp {
1201 fsl,pins =
1202 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
1203 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
1204 };
1205
1206 pinctrl_usb1_vbus: usb1vbusgrp {
1207 fsl,pins =
1208 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */
1209 };
1210
1211 /* USB_1_ID */
1212 pinctrl_usb_1_id: usb1idgrp {
1213 fsl,pins =
1214 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
1215 };
1216
1217 pinctrl_usb2_vbus: usb2vbusgrp {
1218 fsl,pins =
1219 <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */
1220 };
1221
1222 /* On-module Wi-Fi */
1223 pinctrl_usdhc1: usdhc1grp {
1224 fsl,pins =
1225 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>,
1226 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>,
1227 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>,
1228 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>,
1229 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>,
1230 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>;
1231 };
1232
1233 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1234 fsl,pins =
1235 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>,
1236 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>,
1237 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>,
1238 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>,
1239 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>,
1240 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>;
1241 };
1242
1243 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1244 fsl,pins =
1245 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>,
1246 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>,
1247 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>,
1248 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>,
1249 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>,
1250 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>;
1251 };
1252
1253 pinctrl_usdhc2_cd: usdhc2cdgrp {
1254 fsl,pins =
1255 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */
1256 };
1257
1258 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1259 fsl,pins =
1260 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */
1261 };
1262
1263 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1264 fsl,pins =
1265 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */
1266 };
1267
1268 pinctrl_usdhc2: usdhc2grp {
1269 fsl,pins =
1270 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */
1271 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */
1272 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */
1273 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
1274 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
1275 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
1276 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */
1277 };
1278
1279 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1280 fsl,pins =
1281 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1282 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
1283 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
1284 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
1285 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
1286 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
1287 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
1288 };
1289
1290 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1291 fsl,pins =
1292 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1293 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
1294 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
1295 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
1296 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
1297 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
1298 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>;
1299 };
1300
1301 /* Avoid backfeeding with removed card power */
1302 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1303 fsl,pins =
1304 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>,
1305 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>,
1306 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>,
1307 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>,
1308 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>,
1309 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>,
1310 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>;
1311 };
1312
1313 pinctrl_usdhc3: usdhc3grp {
1314 fsl,pins =
1315 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1316 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>,
1317 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
1318 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
1319 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
1320 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
1321 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
1322 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
1323 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
1324 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
1325 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
1326 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>;
1327 };
1328
1329 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1330 fsl,pins =
1331 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1332 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>,
1333 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
1334 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
1335 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
1336 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
1337 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
1338 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
1339 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
1340 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
1341 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
1342 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>;
1343 };
1344
1345 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1346 fsl,pins =
1347 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1348 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>,
1349 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>,
1350 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>,
1351 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>,
1352 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>,
1353 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>,
1354 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>,
1355 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>,
1356 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>,
1357 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
1358 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>;
1359 };
1360
1361 pinctrl_wdog: wdoggrp {
1362 fsl,pins =
1363 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
1364 };
1365
1366 pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1367 fsl,pins =
1368 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */
1369 };
1370
1371 pinctrl_wifi_ctrl: wifictrlgrp {
1372 fsl,pins =
1373 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */
1374 };
1375
1376 pinctrl_wifi_i2s: wifii2sgrp {
1377 fsl,pins =
1378 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */
1379 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */
1380 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */
1381 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */
1382 };
1383
1384 pinctrl_wifi_pwr_en: wifipwrengrp {
1385 fsl,pins =
1386 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */
1387 };
1388 };
