0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2021 Gateworks Corporation
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/input/linux-event-codes.h>
0010 #include <dt-bindings/leds/common.h>
0011
0012 #include "imx8mp.dtsi"
0013
0014 / {
0015 model = "Gateworks Venice GW74xx i.MX8MP board";
0016 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
0017
0018 aliases {
0019 ethernet0 = &eqos;
0020 ethernet1 = &fec;
0021 ethernet2 = &lan1;
0022 ethernet3 = &lan2;
0023 ethernet4 = &lan3;
0024 ethernet5 = &lan4;
0025 ethernet6 = &lan5;
0026 };
0027
0028 chosen {
0029 stdout-path = &uart2;
0030 };
0031
0032 memory@40000000 {
0033 device_type = "memory";
0034 reg = <0x0 0x40000000 0 0x80000000>;
0035 };
0036
0037 gpio-keys {
0038 compatible = "gpio-keys";
0039
0040 key-0 {
0041 label = "user_pb";
0042 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
0043 linux,code = <BTN_0>;
0044 };
0045
0046 key-1 {
0047 label = "user_pb1x";
0048 linux,code = <BTN_1>;
0049 interrupt-parent = <&gsc>;
0050 interrupts = <0>;
0051 };
0052
0053 key-2 {
0054 label = "key_erased";
0055 linux,code = <BTN_2>;
0056 interrupt-parent = <&gsc>;
0057 interrupts = <1>;
0058 };
0059
0060 key-3 {
0061 label = "eeprom_wp";
0062 linux,code = <BTN_3>;
0063 interrupt-parent = <&gsc>;
0064 interrupts = <2>;
0065 };
0066
0067 key-4 {
0068 label = "tamper";
0069 linux,code = <BTN_4>;
0070 interrupt-parent = <&gsc>;
0071 interrupts = <5>;
0072 };
0073
0074 key-5 {
0075 label = "switch_hold";
0076 linux,code = <BTN_5>;
0077 interrupt-parent = <&gsc>;
0078 interrupts = <7>;
0079 };
0080 };
0081
0082 led-controller {
0083 compatible = "gpio-leds";
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_gpio_leds>;
0086
0087 led-0 {
0088 function = LED_FUNCTION_HEARTBEAT;
0089 color = <LED_COLOR_ID_GREEN>;
0090 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
0091 default-state = "on";
0092 linux,default-trigger = "heartbeat";
0093 };
0094
0095 led-1 {
0096 function = LED_FUNCTION_STATUS;
0097 color = <LED_COLOR_ID_RED>;
0098 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
0099 default-state = "off";
0100 };
0101 };
0102
0103 pps {
0104 compatible = "pps-gpio";
0105 pinctrl-names = "default";
0106 pinctrl-0 = <&pinctrl_pps>;
0107 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
0108 };
0109
0110 reg_usb2_vbus: regulator-usb2 {
0111 pinctrl-names = "default";
0112 pinctrl-0 = <&pinctrl_reg_usb2>;
0113 compatible = "regulator-fixed";
0114 regulator-name = "usb_usb2_vbus";
0115 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
0116 enable-active-high;
0117 regulator-min-microvolt = <5000000>;
0118 regulator-max-microvolt = <5000000>;
0119 };
0120
0121 reg_can2_stby: regulator-can2-stby {
0122 compatible = "regulator-fixed";
0123 pinctrl-names = "default";
0124 pinctrl-0 = <&pinctrl_reg_can>;
0125 regulator-name = "can2_stby";
0126 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
0127 regulator-min-microvolt = <3300000>;
0128 regulator-max-microvolt = <3300000>;
0129 };
0130
0131 reg_wifi_en: regulator-wifi-en {
0132 pinctrl-names = "default";
0133 pinctrl-0 = <&pinctrl_reg_wifi>;
0134 compatible = "regulator-fixed";
0135 regulator-name = "wl";
0136 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
0137 startup-delay-us = <100>;
0138 enable-active-high;
0139 regulator-min-microvolt = <1800000>;
0140 regulator-max-microvolt = <1800000>;
0141 };
0142 };
0143
0144 /* off-board header */
0145 &ecspi2 {
0146 pinctrl-names = "default";
0147 pinctrl-0 = <&pinctrl_spi2>;
0148 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0149 status = "okay";
0150 };
0151
0152 &eqos {
0153 pinctrl-names = "default";
0154 pinctrl-0 = <&pinctrl_eqos>;
0155 phy-mode = "rgmii-id";
0156 phy-handle = <ðphy0>;
0157 status = "okay";
0158
0159 mdio {
0160 compatible = "snps,dwmac-mdio";
0161 #address-cells = <1>;
0162 #size-cells = <0>;
0163
0164 ethphy0: ethernet-phy@0 {
0165 compatible = "ethernet-phy-ieee802.3-c22";
0166 reg = <0x0>;
0167 };
0168 };
0169 };
0170
0171 &fec {
0172 pinctrl-names = "default";
0173 pinctrl-0 = <&pinctrl_fec>;
0174 phy-mode = "rgmii-id";
0175 local-mac-address = [00 00 00 00 00 00];
0176 status = "okay";
0177
0178 fixed-link {
0179 speed = <1000>;
0180 full-duplex;
0181 };
0182 };
0183
0184 &flexcan2 {
0185 pinctrl-names = "default";
0186 pinctrl-0 = <&pinctrl_flexcan2>;
0187 xceiver-supply = <®_can2_stby>;
0188 status = "okay";
0189 };
0190
0191 &gpio1 {
0192 gpio-line-names =
0193 "", "", "", "", "", "", "", "",
0194 "", "", "dio0", "", "dio1", "", "", "",
0195 "", "", "", "", "", "", "", "",
0196 "", "", "", "", "", "", "", "";
0197 };
0198
0199 &gpio2 {
0200 gpio-line-names =
0201 "", "", "", "", "", "", "", "",
0202 "", "", "", "", "", "", "", "",
0203 "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "",
0204 "", "", "", "", "", "", "", "";
0205 };
0206
0207 &gpio3 {
0208 gpio-line-names =
0209 "m2_gdis#", "", "", "", "", "", "", "m2_rst#",
0210 "", "", "", "", "", "", "", "",
0211 "m2_off#", "", "", "", "", "", "", "",
0212 "", "", "", "", "", "", "", "";
0213 };
0214
0215 &gpio4 {
0216 gpio-line-names =
0217 "", "", "", "", "", "", "", "",
0218 "", "", "", "", "", "", "", "",
0219 "", "", "", "", "m2_wdis#", "", "", "",
0220 "", "", "", "", "", "", "", "uart_rs485";
0221 };
0222
0223 &gpio5 {
0224 gpio-line-names =
0225 "uart_half", "uart_term", "", "", "", "", "", "",
0226 "", "", "", "", "", "", "", "",
0227 "", "", "", "", "", "", "", "",
0228 "", "", "", "", "", "", "", "";
0229 };
0230
0231 &i2c1 {
0232 clock-frequency = <100000>;
0233 pinctrl-names = "default";
0234 pinctrl-0 = <&pinctrl_i2c1>;
0235 status = "okay";
0236
0237 gsc: gsc@20 {
0238 compatible = "gw,gsc";
0239 reg = <0x20>;
0240 pinctrl-0 = <&pinctrl_gsc>;
0241 interrupt-parent = <&gpio4>;
0242 interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
0243 interrupt-controller;
0244 #interrupt-cells = <1>;
0245
0246 adc {
0247 compatible = "gw,gsc-adc";
0248 #address-cells = <1>;
0249 #size-cells = <0>;
0250
0251 channel@6 {
0252 gw,mode = <0>;
0253 reg = <0x06>;
0254 label = "temp";
0255 };
0256
0257 channel@8 {
0258 gw,mode = <1>;
0259 reg = <0x08>;
0260 label = "vdd_bat";
0261 };
0262
0263 channel@82 {
0264 gw,mode = <2>;
0265 reg = <0x82>;
0266 label = "vdd_adc1";
0267 gw,voltage-divider-ohms = <10000 10000>;
0268 };
0269
0270 channel@84 {
0271 gw,mode = <2>;
0272 reg = <0x84>;
0273 label = "vdd_adc2";
0274 gw,voltage-divider-ohms = <10000 10000>;
0275 };
0276
0277 channel@86 {
0278 gw,mode = <2>;
0279 reg = <0x86>;
0280 label = "vdd_vin";
0281 gw,voltage-divider-ohms = <22100 1000>;
0282 };
0283
0284 channel@88 {
0285 gw,mode = <2>;
0286 reg = <0x88>;
0287 label = "vdd_3p3";
0288 gw,voltage-divider-ohms = <10000 10000>;
0289 };
0290
0291 channel@8c {
0292 gw,mode = <2>;
0293 reg = <0x8c>;
0294 label = "vdd_2p5";
0295 gw,voltage-divider-ohms = <10000 10000>;
0296 };
0297
0298 channel@90 {
0299 gw,mode = <2>;
0300 reg = <0x90>;
0301 label = "vdd_soc";
0302 };
0303
0304 channel@92 {
0305 gw,mode = <2>;
0306 reg = <0x92>;
0307 label = "vdd_arm";
0308 };
0309
0310 channel@98 {
0311 gw,mode = <2>;
0312 reg = <0x98>;
0313 label = "vdd_1p8";
0314 };
0315
0316 channel@9a {
0317 gw,mode = <2>;
0318 reg = <0x9a>;
0319 label = "vdd_1p2";
0320 };
0321
0322 channel@9c {
0323 gw,mode = <2>;
0324 reg = <0x9c>;
0325 label = "vdd_dram";
0326 };
0327
0328 channel@a2 {
0329 gw,mode = <2>;
0330 reg = <0xa2>;
0331 label = "vdd_gsc";
0332 gw,voltage-divider-ohms = <10000 10000>;
0333 };
0334 };
0335 };
0336
0337 gpio: gpio@23 {
0338 compatible = "nxp,pca9555";
0339 reg = <0x23>;
0340 gpio-controller;
0341 #gpio-cells = <2>;
0342 interrupt-parent = <&gsc>;
0343 interrupts = <4>;
0344 };
0345
0346 pmic@25 {
0347 compatible = "nxp,pca9450c";
0348 reg = <0x25>;
0349 pinctrl-names = "default";
0350 pinctrl-0 = <&pinctrl_pmic>;
0351 interrupt-parent = <&gpio3>;
0352 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
0353
0354 regulators {
0355 BUCK1 {
0356 regulator-name = "BUCK1";
0357 regulator-min-microvolt = <720000>;
0358 regulator-max-microvolt = <1000000>;
0359 regulator-boot-on;
0360 regulator-always-on;
0361 regulator-ramp-delay = <3125>;
0362 };
0363
0364 BUCK2 {
0365 regulator-name = "BUCK2";
0366 regulator-min-microvolt = <720000>;
0367 regulator-max-microvolt = <1025000>;
0368 regulator-boot-on;
0369 regulator-always-on;
0370 regulator-ramp-delay = <3125>;
0371 nxp,dvs-run-voltage = <950000>;
0372 nxp,dvs-standby-voltage = <850000>;
0373 };
0374
0375 BUCK4 {
0376 regulator-name = "BUCK4";
0377 regulator-min-microvolt = <3000000>;
0378 regulator-max-microvolt = <3600000>;
0379 regulator-boot-on;
0380 regulator-always-on;
0381 };
0382
0383 BUCK5 {
0384 regulator-name = "BUCK5";
0385 regulator-min-microvolt = <1650000>;
0386 regulator-max-microvolt = <1950000>;
0387 regulator-boot-on;
0388 regulator-always-on;
0389 };
0390
0391 BUCK6 {
0392 regulator-name = "BUCK6";
0393 regulator-min-microvolt = <1045000>;
0394 regulator-max-microvolt = <1155000>;
0395 regulator-boot-on;
0396 regulator-always-on;
0397 };
0398
0399 LDO1 {
0400 regulator-name = "LDO1";
0401 regulator-min-microvolt = <1650000>;
0402 regulator-max-microvolt = <1950000>;
0403 regulator-boot-on;
0404 regulator-always-on;
0405 };
0406
0407 LDO3 {
0408 regulator-name = "LDO3";
0409 regulator-min-microvolt = <1710000>;
0410 regulator-max-microvolt = <1890000>;
0411 regulator-boot-on;
0412 regulator-always-on;
0413 };
0414
0415 LDO5 {
0416 regulator-name = "LDO5";
0417 regulator-min-microvolt = <1800000>;
0418 regulator-max-microvolt = <3300000>;
0419 regulator-boot-on;
0420 regulator-always-on;
0421 };
0422 };
0423 };
0424
0425 eeprom@50 {
0426 compatible = "atmel,24c02";
0427 reg = <0x50>;
0428 pagesize = <16>;
0429 };
0430
0431 eeprom@51 {
0432 compatible = "atmel,24c02";
0433 reg = <0x51>;
0434 pagesize = <16>;
0435 };
0436
0437 eeprom@52 {
0438 compatible = "atmel,24c02";
0439 reg = <0x52>;
0440 pagesize = <16>;
0441 };
0442
0443 eeprom@53 {
0444 compatible = "atmel,24c02";
0445 reg = <0x53>;
0446 pagesize = <16>;
0447 };
0448
0449 rtc@68 {
0450 compatible = "dallas,ds1672";
0451 reg = <0x68>;
0452 };
0453 };
0454
0455 &i2c2 {
0456 clock-frequency = <400000>;
0457 pinctrl-names = "default";
0458 pinctrl-0 = <&pinctrl_i2c2>;
0459 status = "okay";
0460
0461 accelerometer@19 {
0462 compatible = "st,lis2de12";
0463 pinctrl-names = "default";
0464 pinctrl-0 = <&pinctrl_accel>;
0465 reg = <0x19>;
0466 st,drdy-int-pin = <1>;
0467 interrupt-parent = <&gpio1>;
0468 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
0469 interrupt-names = "INT1";
0470 };
0471
0472 switch: switch@5f {
0473 compatible = "microchip,ksz9897";
0474 reg = <0x5f>;
0475 pinctrl-0 = <&pinctrl_ksz>;
0476 interrupt-parent = <&gpio4>;
0477 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
0478
0479 ports {
0480 #address-cells = <1>;
0481 #size-cells = <0>;
0482
0483 lan1: port@0 {
0484 reg = <0>;
0485 label = "lan1";
0486 phy-mode = "internal";
0487 local-mac-address = [00 00 00 00 00 00];
0488 };
0489
0490 lan2: port@1 {
0491 reg = <1>;
0492 label = "lan2";
0493 phy-mode = "internal";
0494 local-mac-address = [00 00 00 00 00 00];
0495 };
0496
0497 lan3: port@2 {
0498 reg = <2>;
0499 label = "lan3";
0500 phy-mode = "internal";
0501 local-mac-address = [00 00 00 00 00 00];
0502 };
0503
0504 lan4: port@3 {
0505 reg = <3>;
0506 label = "lan4";
0507 phy-mode = "internal";
0508 local-mac-address = [00 00 00 00 00 00];
0509 };
0510
0511 lan5: port@4 {
0512 reg = <4>;
0513 label = "lan5";
0514 phy-mode = "internal";
0515 local-mac-address = [00 00 00 00 00 00];
0516 };
0517
0518 port@5 {
0519 reg = <5>;
0520 label = "cpu";
0521 ethernet = <&fec>;
0522 phy-mode = "rgmii-id";
0523
0524 fixed-link {
0525 speed = <1000>;
0526 full-duplex;
0527 };
0528 };
0529 };
0530 };
0531 };
0532
0533 /* off-board header */
0534 &i2c3 {
0535 clock-frequency = <400000>;
0536 pinctrl-names = "default";
0537 pinctrl-0 = <&pinctrl_i2c3>;
0538 status = "okay";
0539 };
0540
0541 /* off-board header */
0542 &i2c4 {
0543 clock-frequency = <400000>;
0544 pinctrl-names = "default";
0545 pinctrl-0 = <&pinctrl_i2c4>;
0546 status = "okay";
0547 };
0548
0549 /* GPS / off-board header */
0550 &uart1 {
0551 pinctrl-names = "default";
0552 pinctrl-0 = <&pinctrl_uart1>;
0553 status = "okay";
0554 };
0555
0556 /* RS232 console */
0557 &uart2 {
0558 pinctrl-names = "default";
0559 pinctrl-0 = <&pinctrl_uart2>;
0560 status = "okay";
0561 };
0562
0563 &uart4 {
0564 pinctrl-names = "default";
0565 pinctrl-0 = <&pinctrl_uart4>;
0566 status = "okay";
0567 };
0568
0569 /* USB1 - Type C front panel */
0570 &usb3_phy0 {
0571 pinctrl-names = "default";
0572 pinctrl-0 = <&pinctrl_usb1>;
0573 status = "okay";
0574 };
0575
0576 &usb3_0 {
0577 fsl,over-current-active-low;
0578 status = "okay";
0579 };
0580
0581 &usb_dwc3_0 {
0582 dr_mode = "host";
0583 status = "okay";
0584 };
0585
0586 /* USB2 - USB3.0 Hub */
0587 &usb3_phy1 {
0588 vbus-supply = <®_usb2_vbus>;
0589 status = "okay";
0590 };
0591
0592 &usb3_1 {
0593 fsl,permanently-attached;
0594 fsl,disable-port-power-control;
0595 status = "okay";
0596 };
0597
0598 &usb_dwc3_1 {
0599 dr_mode = "host";
0600 status = "okay";
0601 };
0602
0603 /* eMMC */
0604 &usdhc3 {
0605 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
0606 assigned-clock-rates = <400000000>;
0607 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0608 pinctrl-0 = <&pinctrl_usdhc3>;
0609 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0610 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0611 bus-width = <8>;
0612 non-removable;
0613 status = "okay";
0614 };
0615
0616 &wdog1 {
0617 pinctrl-names = "default";
0618 pinctrl-0 = <&pinctrl_wdog>;
0619 fsl,ext-reset-output;
0620 status = "okay";
0621 };
0622
0623 &iomuxc {
0624 pinctrl-names = "default";
0625 pinctrl-0 = <&pinctrl_hog>;
0626
0627 pinctrl_hog: hoggrp {
0628 fsl,pins = <
0629 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
0630 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
0631 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */
0632 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */
0633 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
0634 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
0635 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
0636 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
0637 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */
0638 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
0639 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
0640 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
0641 >;
0642 };
0643
0644 pinctrl_accel: accelgrp {
0645 fsl,pins = <
0646 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
0647 >;
0648 };
0649
0650 pinctrl_eqos: eqosgrp {
0651 fsl,pins = <
0652 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
0653 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
0654 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
0655 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
0656 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
0657 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
0658 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
0659 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
0660 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
0661 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
0662 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
0663 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
0664 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
0665 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
0666 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
0667 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
0668 >;
0669 };
0670
0671 pinctrl_fec: fecgrp {
0672 fsl,pins = <
0673 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
0674 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
0675 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
0676 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
0677 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
0678 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
0679 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
0680 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
0681 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
0682 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
0683 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
0684 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
0685 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
0686 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
0687 >;
0688 };
0689
0690 pinctrl_flexcan2: flexcan2grp {
0691 fsl,pins = <
0692 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
0693 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
0694 >;
0695 };
0696
0697 pinctrl_gsc: gscgrp {
0698 fsl,pins = <
0699 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
0700 >;
0701 };
0702
0703 pinctrl_i2c1: i2c1grp {
0704 fsl,pins = <
0705 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
0706 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
0707 >;
0708 };
0709
0710 pinctrl_i2c2: i2c2grp {
0711 fsl,pins = <
0712 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
0713 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
0714 >;
0715 };
0716
0717 pinctrl_i2c3: i2c3grp {
0718 fsl,pins = <
0719 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
0720 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
0721 >;
0722 };
0723
0724 pinctrl_i2c4: i2c4grp {
0725 fsl,pins = <
0726 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
0727 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
0728 >;
0729 };
0730
0731 pinctrl_ksz: kszgrp {
0732 fsl,pins = <
0733 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
0734 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
0735 >;
0736 };
0737
0738 pinctrl_gpio_leds: ledgrp {
0739 fsl,pins = <
0740 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
0741 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
0742 >;
0743 };
0744
0745 pinctrl_pmic: pmicgrp {
0746 fsl,pins = <
0747 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
0748 >;
0749 };
0750
0751 pinctrl_pps: ppsgrp {
0752 fsl,pins = <
0753 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
0754 >;
0755 };
0756
0757 pinctrl_reg_can: regcangrp {
0758 fsl,pins = <
0759 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
0760 >;
0761 };
0762
0763 pinctrl_reg_usb2: regusb2grp {
0764 fsl,pins = <
0765 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
0766 >;
0767 };
0768
0769 pinctrl_reg_wifi: regwifigrp {
0770 fsl,pins = <
0771 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
0772 >;
0773 };
0774
0775 pinctrl_sai2: sai2grp {
0776 fsl,pins = <
0777 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
0778 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
0779 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
0780 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
0781 >;
0782 };
0783
0784 pinctrl_spi2: spi2grp {
0785 fsl,pins = <
0786 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
0787 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
0788 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
0789 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
0790 >;
0791 };
0792
0793 pinctrl_uart1: uart1grp {
0794 fsl,pins = <
0795 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
0796 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
0797 >;
0798 };
0799
0800 pinctrl_uart2: uart2grp {
0801 fsl,pins = <
0802 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
0803 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
0804 >;
0805 };
0806
0807 pinctrl_uart3: uart3grp {
0808 fsl,pins = <
0809 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
0810 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
0811 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
0812 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
0813 >;
0814 };
0815
0816 pinctrl_uart3_gpio: uart3gpiogrp {
0817 fsl,pins = <
0818 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
0819 >;
0820 };
0821
0822 pinctrl_uart4: uart4grp {
0823 fsl,pins = <
0824 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
0825 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
0826 >;
0827 };
0828
0829 pinctrl_usb1: usb1grp {
0830 fsl,pins = <
0831 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
0832 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140
0833 >;
0834 };
0835
0836 pinctrl_usdhc1: usdhc1grp {
0837 fsl,pins = <
0838 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
0839 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
0840 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
0841 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
0842 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
0843 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
0844 >;
0845 };
0846
0847 pinctrl_usdhc3: usdhc3grp {
0848 fsl,pins = <
0849 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
0850 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
0851 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
0852 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
0853 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
0854 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
0855 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
0856 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
0857 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
0858 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
0859 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
0860 >;
0861 };
0862
0863 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0864 fsl,pins = <
0865 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
0866 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
0867 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
0868 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
0869 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
0870 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
0871 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
0872 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
0873 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
0874 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
0875 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
0876 >;
0877 };
0878
0879 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0880 fsl,pins = <
0881 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
0882 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
0883 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
0884 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
0885 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
0886 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
0887 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
0888 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
0889 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
0890 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
0891 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
0892 >;
0893 };
0894
0895 pinctrl_wdog: wdoggrp {
0896 fsl,pins = <
0897 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
0898 >;
0899 };
0900 };
