0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright 2021-2022 TQ-Systems GmbH
0004 * Author: Alexander Stein <alexander.stein@tq-group.com>
0005 */
0006
0007 #include "imx8mp.dtsi"
0008
0009 / {
0010 model = "TQ-Systems i.MX8MPlus TQMa8MPxL";
0011 compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
0012
0013 memory@40000000 {
0014 device_type = "memory";
0015 reg = <0x0 0x40000000 0 0x80000000>;
0016 };
0017
0018 /* identical to buck4_reg, but should never change */
0019 reg_vcc3v3: regulator-vcc3v3 {
0020 compatible = "regulator-fixed";
0021 regulator-name = "VCC3V3";
0022 regulator-min-microvolt = <3300000>;
0023 regulator-max-microvolt = <3300000>;
0024 regulator-always-on;
0025 };
0026
0027 /* e-MMC IO, needed for HS modes */
0028 reg_vcc1v8: regulator-vcc1v8 {
0029 compatible = "regulator-fixed";
0030 regulator-name = "VCC1V8";
0031 regulator-min-microvolt = <1800000>;
0032 regulator-max-microvolt = <1800000>;
0033 regulator-always-on;
0034 };
0035 };
0036
0037 &A53_0 {
0038 cpu-supply = <&buck2_reg>;
0039 };
0040
0041 &flexspi {
0042 pinctrl-names = "default";
0043 pinctrl-0 = <&pinctrl_flexspi0>;
0044 status = "okay";
0045
0046 flash0: flash@0 {
0047 reg = <0>;
0048 #address-cells = <1>;
0049 #size-cells = <1>;
0050 compatible = "jedec,spi-nor";
0051 spi-max-frequency = <80000000>;
0052 spi-tx-bus-width = <1>;
0053 spi-rx-bus-width = <4>;
0054 };
0055 };
0056
0057 &i2c1 {
0058 clock-frequency = <384000>;
0059 pinctrl-names = "default", "gpio";
0060 pinctrl-0 = <&pinctrl_i2c1>;
0061 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0062 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0063 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0064 status = "okay";
0065
0066 /* NXP SE97BTP with temperature sensor + eeprom */
0067 se97: temperature-sensor-eeprom@1b {
0068 compatible = "nxp,se97", "jedec,jc-42.4-temp";
0069 reg = <0x1b>;
0070 };
0071
0072 pmic: pmic@25 {
0073 reg = <0x25>;
0074 compatible = "nxp,pca9450c";
0075
0076 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
0077 pinctrl-0 = <&pinctrl_pmic>;
0078 pinctrl-names = "default";
0079 interrupt-parent = <&gpio1>;
0080 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0081
0082 regulators {
0083 /* V_0V85_SOC: 0.85 .. 0.95 */
0084 buck1_reg: BUCK1 {
0085 regulator-name = "BUCK1";
0086 regulator-min-microvolt = <850000>;
0087 regulator-max-microvolt = <950000>;
0088 regulator-boot-on;
0089 regulator-always-on;
0090 regulator-ramp-delay = <3125>;
0091 };
0092
0093 /* VDD_ARM */
0094 buck2_reg: BUCK2 {
0095 regulator-name = "BUCK2";
0096 regulator-min-microvolt = <850000>;
0097 regulator-max-microvolt = <1000000>;
0098 regulator-boot-on;
0099 regulator-always-on;
0100 nxp,dvs-run-voltage = <950000>;
0101 nxp,dvs-standby-voltage = <850000>;
0102 regulator-ramp-delay = <3125>;
0103 };
0104
0105 /* VCC3V3 -> VMMC, ... must not be changed */
0106 buck4_reg: BUCK4 {
0107 regulator-name = "BUCK4";
0108 regulator-min-microvolt = <3300000>;
0109 regulator-max-microvolt = <3300000>;
0110 regulator-boot-on;
0111 regulator-always-on;
0112 };
0113
0114 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
0115 buck5_reg: BUCK5 {
0116 regulator-name = "BUCK5";
0117 regulator-min-microvolt = <1800000>;
0118 regulator-max-microvolt = <1800000>;
0119 regulator-boot-on;
0120 regulator-always-on;
0121 };
0122
0123 /* V_1V1 -> RAM, ... must not be changed */
0124 buck6_reg: BUCK6 {
0125 regulator-name = "BUCK6";
0126 regulator-min-microvolt = <1100000>;
0127 regulator-max-microvolt = <1100000>;
0128 regulator-boot-on;
0129 regulator-always-on;
0130 };
0131
0132 /* V_1V8_SNVS */
0133 ldo1_reg: LDO1 {
0134 regulator-name = "LDO1";
0135 regulator-min-microvolt = <1800000>;
0136 regulator-max-microvolt = <1800000>;
0137 regulator-boot-on;
0138 regulator-always-on;
0139 };
0140
0141 /* V_1V8_ANA */
0142 ldo3_reg: LDO3 {
0143 regulator-name = "LDO3";
0144 regulator-min-microvolt = <1800000>;
0145 regulator-max-microvolt = <1800000>;
0146 regulator-boot-on;
0147 regulator-always-on;
0148 };
0149
0150 /* unused */
0151 ldo4_reg: LDO4 {
0152 regulator-name = "LDO4";
0153 regulator-min-microvolt = <800000>;
0154 regulator-max-microvolt = <3300000>;
0155 };
0156
0157 /* VCC SD IO - switched using SD2 VSELECT */
0158 ldo5_reg: LDO5 {
0159 regulator-name = "LDO5";
0160 regulator-min-microvolt = <1800000>;
0161 regulator-max-microvolt = <3300000>;
0162 };
0163 };
0164 };
0165
0166 pcf85063: rtc@51 {
0167 compatible = "nxp,pcf85063a";
0168 reg = <0x51>;
0169 };
0170
0171 at24c02: eeprom@53 {
0172 compatible = "nxp,se97b", "atmel,24c02";
0173 read-only;
0174 reg = <0x53>;
0175 pagesize = <16>;
0176 vcc-supply = <®_vcc3v3>;
0177 };
0178
0179 m24c64: eeprom@57 {
0180 compatible = "atmel,24c64";
0181 reg = <0x57>;
0182 pagesize = <32>;
0183 vcc-supply = <®_vcc3v3>;
0184 };
0185 };
0186
0187 &usdhc3 {
0188 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0189 pinctrl-0 = <&pinctrl_usdhc3>;
0190 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0191 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0192 bus-width = <8>;
0193 non-removable;
0194 no-sd;
0195 no-sdio;
0196 vmmc-supply = <®_vcc3v3>;
0197 vqmmc-supply = <®_vcc1v8>;
0198 status = "okay";
0199 };
0200
0201 &wdog1 {
0202 pinctrl-names = "default";
0203 pinctrl-0 = <&pinctrl_wdog>;
0204 fsl,ext-reset-output;
0205 status = "okay";
0206 };
0207
0208 &iomuxc {
0209 pinctrl_flexspi0: flexspi0grp {
0210 fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x142>,
0211 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>,
0212 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>,
0213 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>,
0214 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>,
0215 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>;
0216 };
0217
0218 pinctrl_i2c1: i2c1grp {
0219 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e2>,
0220 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e2>;
0221 };
0222
0223 pinctrl_i2c1_gpio: i2c1-gpiogrp {
0224 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001e2>,
0225 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001e2>;
0226 };
0227
0228 pinctrl_pmic: pmicirqgrp {
0229 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1c0>;
0230 };
0231
0232 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0233 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>;
0234 };
0235
0236 pinctrl_usdhc3: usdhc3grp {
0237 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
0238 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
0239 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
0240 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
0241 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
0242 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
0243 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
0244 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
0245 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
0246 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
0247 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
0248 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
0249 };
0250
0251 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0252 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
0253 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
0254 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
0255 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
0256 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
0257 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
0258 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
0259 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
0260 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
0261 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
0262 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
0263 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
0264 };
0265
0266 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0267 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
0268 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
0269 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
0270 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
0271 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
0272 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
0273 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
0274 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
0275 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
0276 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
0277 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>,
0278 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>;
0279 };
0280
0281 pinctrl_wdog: wdoggrp {
0282 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x1c4>;
0283 };
0284 };
