0001 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
0002 /*
0003 * Copyright 2021-2022 TQ-Systems GmbH
0004 * Author: Alexander Stein <alexander.stein@tq-group.com>
0005 */
0006
0007 /dts-v1/;
0008
0009 #include <dt-bindings/leds/common.h>
0010 #include <dt-bindings/net/ti-dp83867.h>
0011 #include <dt-bindings/pwm/pwm.h>
0012 #include "imx8mp-tqma8mpql.dtsi"
0013
0014 / {
0015 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
0016 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
0017
0018 chosen {
0019 stdout-path = &uart4;
0020 };
0021
0022 iio-hwmon {
0023 compatible = "iio-hwmon";
0024 io-channels = <&adc 0>, <&adc 1>;
0025 };
0026
0027 aliases {
0028 mmc0 = &usdhc3;
0029 mmc1 = &usdhc2;
0030 mmc2 = &usdhc1;
0031 rtc0 = &pcf85063;
0032 rtc1 = &snvs_rtc;
0033 spi0 = &flexspi;
0034 spi1 = &ecspi1;
0035 spi2 = &ecspi2;
0036 spi3 = &ecspi3;
0037 };
0038
0039 backlight_lvds: backlight {
0040 compatible = "pwm-backlight";
0041 pinctrl-names = "default";
0042 pinctrl-0 = <&pinctrl_backlight>;
0043 pwms = <&pwm2 0 5000000 0>;
0044 brightness-levels = <0 4 8 16 32 64 128 255>;
0045 default-brightness-level = <7>;
0046 power-supply = <®_vcc_12v0>;
0047 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
0048 status = "disabled";
0049 };
0050
0051 gpio-keys {
0052 compatible = "gpio-keys";
0053 pinctrl-names = "default";
0054 pinctrl-0 = <&pinctrl_gpiobutton>;
0055 autorepeat;
0056
0057 switch-1 {
0058 label = "S12";
0059 linux,code = <BTN_0>;
0060 gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
0061 };
0062
0063 switch-2 {
0064 label = "S13";
0065 linux,code = <BTN_1>;
0066 gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
0067 };
0068 };
0069
0070 gpio-leds {
0071 compatible = "gpio-leds";
0072 pinctrl-names = "default";
0073 pinctrl-0 = <&pinctrl_gpioled>;
0074
0075 led-0 {
0076 color = <LED_COLOR_ID_GREEN>;
0077 function = LED_FUNCTION_STATUS;
0078 function-enumerator = <0>;
0079 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
0080 linux,default-trigger = "default-on";
0081 };
0082
0083 led-1 {
0084 color = <LED_COLOR_ID_GREEN>;
0085 function = LED_FUNCTION_HEARTBEAT;
0086 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
0087 linux,default-trigger = "heartbeat";
0088 };
0089
0090 led-2 {
0091 color = <LED_COLOR_ID_YELLOW>;
0092 function = LED_FUNCTION_STATUS;
0093 function-enumerator = <1>;
0094 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
0095 };
0096 };
0097
0098 display: display {
0099 /*
0100 * Display is not fixed, so compatible has to be added from
0101 * DT overlay
0102 */
0103 pinctrl-names = "default";
0104 pinctrl-0 = <&pinctrl_lvdsdisplay>;
0105 power-supply = <®_vcc_3v3>;
0106 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
0107 backlight = <&backlight_lvds>;
0108 status = "disabled";
0109 };
0110
0111 reg_usdhc2_vmmc: regulator-usdhc2 {
0112 compatible = "regulator-fixed";
0113 pinctrl-names = "default";
0114 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
0115 regulator-name = "VSD_3V3";
0116 regulator-min-microvolt = <3300000>;
0117 regulator-max-microvolt = <3300000>;
0118 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0119 enable-active-high;
0120 startup-delay-us = <100>;
0121 off-on-delay-us = <12000>;
0122 };
0123
0124 reg_vcc_12v0: regulator-12v0 {
0125 compatible = "regulator-fixed";
0126 pinctrl-names = "default";
0127 pinctrl-0 = <&pinctrl_reg12v0>;
0128 regulator-name = "VCC_12V0";
0129 regulator-min-microvolt = <12000000>;
0130 regulator-max-microvolt = <12000000>;
0131 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
0132 enable-active-high;
0133 };
0134
0135 reg_vcc_3v3: regulator-3v3 {
0136 compatible = "regulator-fixed";
0137 regulator-name = "VCC_3V3";
0138 regulator-min-microvolt = <3300000>;
0139 regulator-max-microvolt = <3300000>;
0140 };
0141
0142 reserved-memory {
0143 #address-cells = <2>;
0144 #size-cells = <2>;
0145 ranges;
0146
0147 ocram: ocram@900000 {
0148 no-map;
0149 reg = <0 0x900000 0 0x70000>;
0150 };
0151
0152 /* global autoconfigured region for contiguous allocations */
0153 linux,cma {
0154 compatible = "shared-dma-pool";
0155 reusable;
0156 size = <0 0x38000000>;
0157 alloc-ranges = <0 0x40000000 0 0xB0000000>;
0158 linux,cma-default;
0159 };
0160 };
0161 };
0162
0163 &ecspi1 {
0164 pinctrl-names = "default";
0165 pinctrl-0 = <&pinctrl_ecspi1>;
0166 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
0167 status = "okay";
0168 };
0169
0170 &ecspi2 {
0171 pinctrl-names = "default";
0172 pinctrl-0 = <&pinctrl_ecspi2>;
0173 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0174 status = "okay";
0175 };
0176
0177 &ecspi3 {
0178 pinctrl-names = "default";
0179 pinctrl-0 = <&pinctrl_ecspi3>;
0180 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
0181 status = "okay";
0182
0183 adc: adc@0 {
0184 reg = <0>;
0185 compatible = "microchip,mcp3202";
0186 /* 100 ksps * 18 */
0187 spi-max-frequency = <1800000>;
0188 vref-supply = <®_vcc_3v3>;
0189 #io-channel-cells = <1>;
0190 };
0191 };
0192
0193 &eqos {
0194 pinctrl-names = "default";
0195 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>;
0196 phy-mode = "rgmii-id";
0197 phy-handle = <ðphy3>;
0198 status = "okay";
0199
0200 mdio {
0201 compatible = "snps,dwmac-mdio";
0202 #address-cells = <1>;
0203 #size-cells = <0>;
0204
0205 ethphy3: ethernet-phy@3 {
0206 compatible = "ethernet-phy-ieee802.3-c22";
0207 reg = <3>;
0208 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0209 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0210 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0211 ti,dp83867-rxctrl-strap-quirk;
0212 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
0213 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
0214 reset-assert-us = <500000>;
0215 reset-deassert-us = <50000>;
0216 enet-phy-lane-no-swap;
0217 interrupt-parent = <&gpio4>;
0218 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
0219 };
0220 };
0221 };
0222
0223 &fec {
0224 pinctrl-names = "default";
0225 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>;
0226 phy-mode = "rgmii-id";
0227 phy-handle = <ðphy0>;
0228 fsl,magic-packet;
0229 status = "okay";
0230
0231 mdio {
0232 #address-cells = <1>;
0233 #size-cells = <0>;
0234
0235 ethphy0: ethernet-phy@0 {
0236 compatible = "ethernet-phy-ieee802.3-c22";
0237 reg = <0>;
0238 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0239 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
0240 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0241 ti,dp83867-rxctrl-strap-quirk;
0242 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
0243 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
0244 reset-assert-us = <500000>;
0245 reset-deassert-us = <50000>;
0246 enet-phy-lane-no-swap;
0247 interrupt-parent = <&gpio4>;
0248 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
0249 };
0250 };
0251 };
0252
0253 &flexcan1 {
0254 pinctrl-names = "default";
0255 pinctrl-0 = <&pinctrl_flexcan1>;
0256 xceiver-supply = <®_vcc_3v3>;
0257 status = "okay";
0258 };
0259
0260 &flexcan2 {
0261 pinctrl-names = "default";
0262 pinctrl-0 = <&pinctrl_flexcan2>;
0263 xceiver-supply = <®_vcc_3v3>;
0264 status = "okay";
0265 };
0266
0267 &gpio1 {
0268 pinctrl-names = "default";
0269 pinctrl-0 = <&pinctrl_gpio1>;
0270
0271 gpio-line-names = "GPO1", "GPO0", "", "GPO3",
0272 "", "", "GPO2", "GPI0",
0273 "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#",
0274 "OTG_PWR", "", "GPI2", "GPI3",
0275 "", "", "", "",
0276 "", "", "", "",
0277 "", "", "", "",
0278 "", "", "", "";
0279 };
0280
0281 &gpio2 {
0282 pinctrl-names = "default";
0283 pinctrl-0 = <&pinctrl_hoggpio2>;
0284
0285 gpio-line-names = "", "", "", "",
0286 "", "", "VCC12V_EN", "PERST#",
0287 "", "", "CLKREQ#", "PEWAKE#",
0288 "USDHC2_CD", "", "", "",
0289 "", "", "", "V_SD3V3_EN",
0290 "", "", "", "",
0291 "", "", "", "",
0292 "", "", "", "";
0293
0294 perst-hog {
0295 gpio-hog;
0296 gpios = <7 0>;
0297 output-high;
0298 line-name = "PERST#";
0299 };
0300
0301 clkreq-hog {
0302 gpio-hog;
0303 gpios = <10 0>;
0304 input;
0305 line-name = "CLKREQ#";
0306 };
0307
0308 pewake-hog {
0309 gpio-hog;
0310 gpios = <11 0>;
0311 input;
0312 line-name = "PEWAKE#";
0313 };
0314 };
0315
0316 &gpio3 {
0317 gpio-line-names = "", "", "", "",
0318 "", "", "", "",
0319 "", "", "", "",
0320 "", "", "LVDS0_RESET#", "",
0321 "", "", "", "LVDS0_BLT_EN",
0322 "LVDS0_PWR_EN", "", "", "",
0323 "", "", "", "",
0324 "", "", "", "";
0325 };
0326
0327 &gpio4 {
0328 pinctrl-names = "default";
0329 pinctrl-0 = <&pinctrl_gpio4>;
0330
0331 gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#",
0332 "", "", "", "",
0333 "", "", "", "",
0334 "", "", "", "",
0335 "", "", "DP_IRQ", "DSI_EN",
0336 "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "",
0337 "", "", "", "FAN_PWR",
0338 "RTC_EVENT#", "CODEC_RST#", "", "";
0339 };
0340
0341 &gpio5 {
0342 gpio-line-names = "", "", "", "LED2",
0343 "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC",
0344 "CSI0_TRIGGER", "CSI0_ENABLE", "", "",
0345 "", "ECSPI2_SS0", "", "",
0346 "", "", "", "",
0347 "", "", "", "",
0348 "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B",
0349 "", "", "", "";
0350 };
0351
0352 &i2c2 {
0353 clock-frequency = <384000>;
0354 pinctrl-names = "default", "gpio";
0355 pinctrl-0 = <&pinctrl_i2c2>;
0356 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0357 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0358 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0359 status = "okay";
0360
0361 /* NXP SE97BTP with temperature sensor + eeprom */
0362 se97_1c: temperature-sensor-eeprom@1c {
0363 compatible = "nxp,se97", "jedec,jc-42.4-temp";
0364 reg = <0x1c>;
0365 };
0366
0367 at24c02_54: eeprom@54 {
0368 compatible = "nxp,se97b", "atmel,24c02";
0369 reg = <0x54>;
0370 pagesize = <16>;
0371 vcc-supply = <®_vcc_3v3>;
0372 };
0373 };
0374
0375 &i2c4 {
0376 clock-frequency = <384000>;
0377 pinctrl-names = "default", "gpio";
0378 pinctrl-0 = <&pinctrl_i2c4>;
0379 pinctrl-1 = <&pinctrl_i2c4_gpio>;
0380 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0381 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0382 status = "okay";
0383 };
0384
0385 &i2c6 {
0386 clock-frequency = <384000>;
0387 pinctrl-names = "default", "gpio";
0388 pinctrl-0 = <&pinctrl_i2c6>;
0389 pinctrl-1 = <&pinctrl_i2c6_gpio>;
0390 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0391 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0392 status = "okay";
0393 };
0394
0395 &pcf85063 {
0396 /* RTC_EVENT# is connected on MBa8MPxL */
0397 pinctrl-names = "default";
0398 pinctrl-0 = <&pinctrl_pcf85063>;
0399 interrupt-parent = <&gpio4>;
0400 interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
0401 };
0402
0403 &pwm2 {
0404 pinctrl-names = "default";
0405 pinctrl-0 = <&pinctrl_pwm2>;
0406 status = "disabled";
0407 };
0408
0409 &pwm3 {
0410 pinctrl-names = "default";
0411 pinctrl-0 = <&pinctrl_pwm3>;
0412 status = "okay";
0413 };
0414
0415 &snvs_pwrkey {
0416 status = "okay";
0417 };
0418
0419 &uart1 {
0420 pinctrl-names = "default";
0421 pinctrl-0 = <&pinctrl_uart1>;
0422 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
0423 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
0424 status = "okay";
0425 };
0426
0427 &uart2 {
0428 pinctrl-names = "default";
0429 pinctrl-0 = <&pinctrl_uart2>;
0430 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
0431 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
0432 status = "okay";
0433 };
0434
0435 &uart3 {
0436 pinctrl-names = "default";
0437 pinctrl-0 = <&pinctrl_uart3>;
0438 assigned-clocks = <&clk IMX8MP_CLK_UART3>;
0439 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
0440 status = "okay";
0441 };
0442
0443 &uart4 {
0444 /* console */
0445 pinctrl-names = "default";
0446 pinctrl-0 = <&pinctrl_uart4>;
0447 status = "okay";
0448 };
0449
0450 &usdhc2 {
0451 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0452 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0453 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0454 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0455 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0456 vmmc-supply = <®_usdhc2_vmmc>;
0457 no-mmc;
0458 no-sdio;
0459 disable-wp;
0460 bus-width = <4>;
0461 status = "okay";
0462 };
0463
0464 &iomuxc {
0465 pinctrl_backlight: backlightgrp {
0466 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>;
0467 };
0468
0469 pinctrl_flexcan1: flexcan1grp {
0470 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>,
0471 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>;
0472 };
0473
0474 pinctrl_flexcan2: flexcan2grp {
0475 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>,
0476 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>;
0477 };
0478
0479 /* only on X57, primary used as CSI0 control signals */
0480 pinctrl_ecspi1: ecspi1grp {
0481 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>,
0482 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>,
0483 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>,
0484 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>;
0485 };
0486
0487 /* on X63 and optionally on X57, can also be used as CSI1 control signals */
0488 pinctrl_ecspi2: ecspi2grp {
0489 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>,
0490 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>,
0491 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>,
0492 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>;
0493 };
0494
0495 pinctrl_ecspi3: ecspi3grp {
0496 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>,
0497 <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>,
0498 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>,
0499 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>;
0500 };
0501
0502 pinctrl_eqos: eqosgrp {
0503 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>,
0504 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>,
0505 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>,
0506 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>,
0507 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>,
0508 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>,
0509 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>,
0510 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>,
0511 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>,
0512 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>,
0513 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
0514 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
0515 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
0516 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
0517 };
0518
0519 pinctrl_eqos_event: eqosevtgrp {
0520 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>,
0521 <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>;
0522 };
0523
0524 pinctrl_eqos_phy: eqosphygrp {
0525 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>,
0526 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>;
0527 };
0528
0529 pinctrl_fec: fecgrp {
0530 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>,
0531 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>,
0532 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>,
0533 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>,
0534 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>,
0535 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>,
0536 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>,
0537 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>,
0538 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>,
0539 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>,
0540 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>,
0541 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>,
0542 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>,
0543 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>;
0544 };
0545
0546 pinctrl_fec_event: fecevtgrp {
0547 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>,
0548 <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>;
0549 };
0550
0551 pinctrl_fec_phy: fecphygrp {
0552 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>,
0553 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>;
0554 };
0555
0556 pinctrl_fec_phyalt: fecphyaltgrp {
0557 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>,
0558 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>;
0559 };
0560
0561 pinctrl_gpiobutton: gpiobuttongrp {
0562 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>,
0563 <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>;
0564 };
0565
0566 pinctrl_gpioled: gpioledgrp {
0567 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>,
0568 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>,
0569 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>;
0570 };
0571
0572 pinctrl_gpio1: gpio1grp {
0573 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>,
0574 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>,
0575 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>,
0576 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>,
0577 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>,
0578 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>,
0579 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>,
0580 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>;
0581 };
0582
0583 pinctrl_gpio4: gpio4grp {
0584 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>,
0585 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>;
0586 };
0587
0588 pinctrl_hdmi: hdmigrp {
0589 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
0590 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
0591 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>,
0592 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>;
0593 };
0594
0595 pinctrl_hoggpio2: hoggpio2grp {
0596 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>,
0597 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>,
0598 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>;
0599 };
0600
0601 pinctrl_i2c2: i2c2grp {
0602 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>,
0603 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>;
0604 };
0605
0606 pinctrl_i2c2_gpio: i2c2-gpiogrp {
0607 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>,
0608 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>;
0609 };
0610
0611 pinctrl_i2c4: i2c4grp {
0612 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>,
0613 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>;
0614 };
0615
0616 pinctrl_i2c4_gpio: i2c4-gpiogrp {
0617 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>,
0618 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>;
0619 };
0620
0621 pinctrl_i2c6: i2c6grp {
0622 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>,
0623 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>;
0624 };
0625
0626 pinctrl_i2c6_gpio: i2c6-gpiogrp {
0627 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>,
0628 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>;
0629 };
0630
0631 pinctrl_lvdsdisplay: lvdsdisplaygrp {
0632 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */
0633 };
0634
0635 pinctrl_pcf85063: pcf85063grp {
0636 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>;
0637 };
0638
0639 /* LVDS Backlight */
0640 pinctrl_pwm2: pwm2grp {
0641 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>;
0642 };
0643
0644 /* FAN */
0645 pinctrl_pwm3: pwm3grp {
0646 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>;
0647 };
0648
0649 pinctrl_reg12v0: reg12v0grp {
0650 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */
0651 };
0652
0653 /* X61 */
0654 pinctrl_uart1: uart1grp {
0655 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>,
0656 <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>;
0657 };
0658
0659 /* X61 */
0660 pinctrl_uart2: uart2grp {
0661 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>,
0662 <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>;
0663 };
0664
0665 pinctrl_uart3: uart3grp {
0666 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>,
0667 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>;
0668 };
0669
0670 pinctrl_uart4: uart4grp {
0671 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>,
0672 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>;
0673 };
0674
0675 pinctrl_usdhc2: usdhc2grp {
0676 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
0677 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
0678 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
0679 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
0680 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
0681 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
0682 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
0683 };
0684
0685 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0686 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
0687 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
0688 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
0689 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
0690 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
0691 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
0692 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
0693 };
0694
0695 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0696 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
0697 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
0698 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
0699 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
0700 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
0701 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
0702 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
0703 };
0704
0705 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
0706 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>;
0707 };
0708 };
