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OSCL-LXR

 
 

    


0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2020 PHYTEC Messtechnik GmbH
0004  * Author: Teresa Remmet <t.remmet@phytec.de>
0005  */
0006 
0007 #include <dt-bindings/net/ti-dp83867.h>
0008 #include "imx8mp.dtsi"
0009 
0010 / {
0011         model = "PHYTEC phyCORE-i.MX8MP";
0012         compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
0013 
0014         aliases {
0015                 rtc0 = &rv3028;
0016                 rtc1 = &snvs_rtc;
0017         };
0018 
0019         memory@40000000 {
0020                 device_type = "memory";
0021                 reg = <0x0 0x40000000 0 0x80000000>;
0022         };
0023 };
0024 
0025 &A53_0 {
0026         cpu-supply = <&buck2>;
0027 };
0028 
0029 &A53_1 {
0030         cpu-supply = <&buck2>;
0031 };
0032 
0033 &A53_2 {
0034         cpu-supply = <&buck2>;
0035 };
0036 
0037 &A53_3 {
0038         cpu-supply = <&buck2>;
0039 };
0040 
0041 /* ethernet 1 */
0042 &fec {
0043         pinctrl-names = "default";
0044         pinctrl-0 = <&pinctrl_fec>;
0045         phy-mode = "rgmii-id";
0046         phy-handle = <&ethphy1>;
0047         fsl,magic-packet;
0048         status = "okay";
0049 
0050         mdio {
0051                 #address-cells = <1>;
0052                 #size-cells = <0>;
0053 
0054                 ethphy1: ethernet-phy@0 {
0055                         compatible = "ethernet-phy-ieee802.3-c22";
0056                         reg = <0>;
0057                         interrupt-parent = <&gpio1>;
0058                         interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
0059                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0060                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
0061                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0062                         ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
0063                         ti,min-output-impedance;
0064                         enet-phy-lane-no-swap;
0065                 };
0066         };
0067 };
0068 
0069 &flexspi {
0070         pinctrl-names = "default";
0071         pinctrl-0 = <&pinctrl_flexspi0>;
0072         status = "okay";
0073 
0074         som_flash: flash@0 {
0075                 compatible = "jedec,spi-nor";
0076                 reg = <0>;
0077                 spi-max-frequency = <80000000>;
0078                 spi-tx-bus-width = <1>;
0079                 spi-rx-bus-width = <4>;
0080         };
0081 };
0082 
0083 &i2c1 {
0084         clock-frequency = <400000>;
0085         pinctrl-names = "default", "gpio";
0086         pinctrl-0 = <&pinctrl_i2c1>;
0087         pinctrl-1 = <&pinctrl_i2c1_gpio>;
0088         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0089         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0090         status = "okay";
0091 
0092         pmic: pmic@25 {
0093                 reg = <0x25>;
0094                 compatible = "nxp,pca9450c";
0095                 pinctrl-names = "default";
0096                 pinctrl-0 = <&pinctrl_pmic>;
0097                 interrupt-parent = <&gpio4>;
0098                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
0099 
0100                 regulators {
0101                         buck1: BUCK1 {
0102                                 regulator-compatible = "BUCK1";
0103                                 regulator-min-microvolt = <600000>;
0104                                 regulator-max-microvolt = <2187500>;
0105                                 regulator-boot-on;
0106                                 regulator-always-on;
0107                                 regulator-ramp-delay = <3125>;
0108                         };
0109 
0110                         buck2: BUCK2 {
0111                                 regulator-compatible = "BUCK2";
0112                                 regulator-min-microvolt = <600000>;
0113                                 regulator-max-microvolt = <2187500>;
0114                                 regulator-boot-on;
0115                                 regulator-always-on;
0116                                 regulator-ramp-delay = <3125>;
0117                                 nxp,dvs-run-voltage = <950000>;
0118                                 nxp,dvs-standby-voltage = <850000>;
0119                         };
0120 
0121                         buck4: BUCK4 {
0122                                 regulator-compatible = "BUCK4";
0123                                 regulator-min-microvolt = <600000>;
0124                                 regulator-max-microvolt = <3400000>;
0125                                 regulator-boot-on;
0126                                 regulator-always-on;
0127                         };
0128 
0129                         buck5: BUCK5 {
0130                                 regulator-compatible = "BUCK5";
0131                                 regulator-min-microvolt = <600000>;
0132                                 regulator-max-microvolt = <3400000>;
0133                                 regulator-boot-on;
0134                                 regulator-always-on;
0135                         };
0136 
0137                         buck6: BUCK6 {
0138                                 regulator-compatible = "BUCK6";
0139                                 regulator-min-microvolt = <600000>;
0140                                 regulator-max-microvolt = <3400000>;
0141                                 regulator-boot-on;
0142                                 regulator-always-on;
0143                         };
0144 
0145                         ldo1: LDO1 {
0146                                 regulator-compatible = "LDO1";
0147                                 regulator-min-microvolt = <1600000>;
0148                                 regulator-max-microvolt = <3300000>;
0149                                 regulator-boot-on;
0150                                 regulator-always-on;
0151                         };
0152 
0153                         ldo2: LDO2 {
0154                                 regulator-compatible = "LDO2";
0155                                 regulator-min-microvolt = <800000>;
0156                                 regulator-max-microvolt = <1150000>;
0157                                 regulator-boot-on;
0158                                 regulator-always-on;
0159                         };
0160 
0161                         ldo3: LDO3 {
0162                                 regulator-compatible = "LDO3";
0163                                 regulator-min-microvolt = <800000>;
0164                                 regulator-max-microvolt = <3300000>;
0165                                 regulator-boot-on;
0166                                 regulator-always-on;
0167                         };
0168 
0169                         ldo4: LDO4 {
0170                                 regulator-compatible = "LDO4";
0171                                 regulator-min-microvolt = <800000>;
0172                                 regulator-max-microvolt = <3300000>;
0173                         };
0174 
0175                         ldo5: LDO5 {
0176                                 regulator-compatible = "LDO5";
0177                                 regulator-min-microvolt = <1800000>;
0178                                 regulator-max-microvolt = <3300000>;
0179                                 regulator-boot-on;
0180                                 regulator-always-on;
0181                         };
0182                 };
0183         };
0184 
0185         eeprom@51 {
0186                 compatible = "atmel,24c32";
0187                 reg = <0x51>;
0188                 pagesize = <32>;
0189         };
0190 
0191         rv3028: rtc@52 {
0192                 compatible = "microcrystal,rv3028";
0193                 reg = <0x52>;
0194                 trickle-resistor-ohms = <3000>;
0195         };
0196 };
0197 
0198 /* eMMC */
0199 &usdhc3 {
0200         assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
0201         assigned-clock-rates = <400000000>;
0202         pinctrl-names = "default", "state_100mhz", "state_200mhz";
0203         pinctrl-0 = <&pinctrl_usdhc3>;
0204         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0205         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0206         bus-width = <8>;
0207         non-removable;
0208         status = "okay";
0209 };
0210 
0211 &wdog1 {
0212         pinctrl-names = "default";
0213         pinctrl-0 = <&pinctrl_wdog>;
0214         fsl,ext-reset-output;
0215         status = "okay";
0216 };
0217 
0218 &iomuxc {
0219         pinctrl_fec: fecgrp {
0220                 fsl,pins = <
0221                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
0222                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
0223                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
0224                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
0225                         MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x91
0226                         MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x91
0227                         MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x91
0228                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
0229                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x12
0230                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x12
0231                         MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x14
0232                         MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x14
0233                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x14
0234                         MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x14
0235                         MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15             0x11
0236                 >;
0237         };
0238 
0239         pinctrl_flexspi0: flexspi0grp {
0240                 fsl,pins = <
0241                         MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
0242                         MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
0243                         MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
0244                         MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
0245                         MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
0246                         MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
0247                 >;
0248         };
0249 
0250         pinctrl_i2c1: i2c1grp {
0251                 fsl,pins = <
0252                         MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL         0x400001c3
0253                         MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA         0x400001c3
0254                 >;
0255         };
0256 
0257         pinctrl_i2c1_gpio: i2c1gpiogrp {
0258                 fsl,pins = <
0259                         MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14       0x1e3
0260                         MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15       0x1e3
0261                 >;
0262         };
0263 
0264         pinctrl_pmic: pmicirqgrp {
0265                 fsl,pins = <
0266                         MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18      0x141
0267                 >;
0268         };
0269 
0270         pinctrl_usdhc3: usdhc3grp {
0271                 fsl,pins = <
0272                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
0273                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
0274                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
0275                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
0276                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
0277                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
0278                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
0279                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
0280                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
0281                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
0282                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
0283                 >;
0284         };
0285 
0286         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0287                 fsl,pins = <
0288                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
0289                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
0290                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
0291                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
0292                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
0293                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
0294                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
0295                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
0296                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
0297                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
0298                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
0299                 >;
0300         };
0301 
0302         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0303                 fsl,pins = <
0304                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
0305                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
0306                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d2
0307                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d2
0308                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d2
0309                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d2
0310                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d2
0311                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d2
0312                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d2
0313                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d2
0314                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
0315                 >;
0316         };
0317 
0318         pinctrl_wdog: wdoggrp {
0319                 fsl,pins = <
0320                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0xe6
0321                 >;
0322         };
0323 };