0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
0004 * Author: Teresa Remmet <t.remmet@phytec.de>
0005 */
0006
0007 /dts-v1/;
0008
0009 #include <dt-bindings/leds/leds-pca9532.h>
0010 #include <dt-bindings/pwm/pwm.h>
0011 #include "imx8mp-phycore-som.dtsi"
0012
0013 / {
0014 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
0015 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
0016 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
0017
0018 chosen {
0019 stdout-path = &uart1;
0020 };
0021
0022 reg_usdhc2_vmmc: regulator-usdhc2 {
0023 compatible = "regulator-fixed";
0024 pinctrl-names = "default";
0025 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
0026 regulator-name = "VSD_3V3";
0027 regulator-min-microvolt = <3300000>;
0028 regulator-max-microvolt = <3300000>;
0029 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0030 enable-active-high;
0031 startup-delay-us = <100>;
0032 off-on-delay-us = <12000>;
0033 };
0034 };
0035
0036 &eqos {
0037 pinctrl-names = "default";
0038 pinctrl-0 = <&pinctrl_eqos>;
0039 phy-mode = "rgmii-id";
0040 phy-handle = <ðphy0>;
0041 status = "okay";
0042
0043 mdio {
0044 compatible = "snps,dwmac-mdio";
0045 #address-cells = <1>;
0046 #size-cells = <0>;
0047
0048 ethphy0: ethernet-phy@1 {
0049 compatible = "ethernet-phy-ieee802.3-c22";
0050 reg = <0x1>;
0051 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
0052 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
0053 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
0054 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
0055 enet-phy-lane-no-swap;
0056 };
0057 };
0058 };
0059
0060 &i2c2 {
0061 clock-frequency = <400000>;
0062 pinctrl-names = "default", "gpio";
0063 pinctrl-0 = <&pinctrl_i2c2>;
0064 pinctrl-1 = <&pinctrl_i2c2_gpio>;
0065 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0066 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0067 status = "okay";
0068
0069 eeprom@51 {
0070 compatible = "atmel,24c02";
0071 reg = <0x51>;
0072 pagesize = <16>;
0073 };
0074
0075 leds@62 {
0076 compatible = "nxp,pca9533";
0077 reg = <0x62>;
0078
0079 led1 {
0080 type = <PCA9532_TYPE_LED>;
0081 };
0082
0083 led2 {
0084 type = <PCA9532_TYPE_LED>;
0085 };
0086
0087 led3 {
0088 type = <PCA9532_TYPE_LED>;
0089 };
0090 };
0091 };
0092
0093 &snvs_pwrkey {
0094 status = "okay";
0095 };
0096
0097 /* debug console */
0098 &uart1 {
0099 pinctrl-names = "default";
0100 pinctrl-0 = <&pinctrl_uart1>;
0101 status = "okay";
0102 };
0103
0104 /* SD-Card */
0105 &usdhc2 {
0106 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0107 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
0108 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
0109 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
0110 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0111 vmmc-supply = <®_usdhc2_vmmc>;
0112 bus-width = <4>;
0113 status = "okay";
0114 };
0115
0116 &iomuxc {
0117 pinctrl_eqos: eqosgrp {
0118 fsl,pins = <
0119 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
0120 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
0121 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
0122 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
0123 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
0124 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
0125 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
0126 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
0127 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
0128 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
0129 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
0130 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
0131 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
0132 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
0133 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
0134 >;
0135 };
0136
0137 pinctrl_i2c2: i2c2grp {
0138 fsl,pins = <
0139 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
0140 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
0141 >;
0142 };
0143
0144 pinctrl_i2c2_gpio: i2c2gpiogrp {
0145 fsl,pins = <
0146 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
0147 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
0148 >;
0149 };
0150
0151 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0152 fsl,pins = <
0153 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
0154 >;
0155 };
0156
0157 pinctrl_uart1: uart1grp {
0158 fsl,pins = <
0159 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
0160 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
0161 >;
0162 };
0163
0164 pinctrl_usdhc2_pins: usdhc2-gpiogrp {
0165 fsl,pins = <
0166 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
0167 >;
0168 };
0169
0170 pinctrl_usdhc2: usdhc2grp {
0171 fsl,pins = <
0172 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
0173 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
0174 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
0175 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
0176 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
0177 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
0178 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
0179 >;
0180 };
0181
0182 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0183 fsl,pins = <
0184 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
0185 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
0186 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
0187 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
0188 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
0189 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
0190 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
0191 >;
0192 };
0193
0194 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0195 fsl,pins = <
0196 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
0197 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
0198 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
0199 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
0200 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
0201 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
0202 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
0203 >;
0204 };
0205 };
