0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
0004 */
0005
0006 #include "imx8mp.dtsi"
0007
0008 / {
0009 model = "DH electronics i.MX8M Plus DHCOM SoM";
0010 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
0011
0012 aliases {
0013 ethernet0 = &eqos;
0014 ethernet1 = &fec;
0015 rtc0 = &rv3032;
0016 rtc1 = &snvs_rtc;
0017 spi0 = &flexspi;
0018 };
0019
0020 memory@40000000 {
0021 device_type = "memory";
0022 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
0023 reg = <0x0 0x40000000 0 0x08000000>;
0024 };
0025
0026 reg_eth_vio: regulator-eth-vio {
0027 compatible = "regulator-fixed";
0028 gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
0029 pinctrl-0 = <&pinctrl_enet_vio>;
0030 pinctrl-names = "default";
0031 regulator-always-on;
0032 regulator-boot-on;
0033 regulator-min-microvolt = <3300000>;
0034 regulator-max-microvolt = <3300000>;
0035 regulator-name = "eth_vio";
0036 vin-supply = <&buck4>;
0037 };
0038
0039 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
0040 compatible = "regulator-fixed";
0041 enable-active-high;
0042 gpio = <&gpio2 19 0>; /* SD2_RESET */
0043 off-on-delay-us = <12000>;
0044 pinctrl-names = "default";
0045 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
0046 regulator-max-microvolt = <3300000>;
0047 regulator-min-microvolt = <3300000>;
0048 regulator-name = "VDD_3V3_SD";
0049 startup-delay-us = <100>;
0050 vin-supply = <&buck4>;
0051 };
0052 };
0053
0054 &A53_0 {
0055 cpu-supply = <&buck2>;
0056 };
0057
0058 &A53_1 {
0059 cpu-supply = <&buck2>;
0060 };
0061
0062 &A53_2 {
0063 cpu-supply = <&buck2>;
0064 };
0065
0066 &A53_3 {
0067 cpu-supply = <&buck2>;
0068 };
0069
0070 &ecspi1 {
0071 pinctrl-names = "default";
0072 pinctrl-0 = <&pinctrl_ecspi1>;
0073 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
0074 status = "disabled";
0075 };
0076
0077 &ecspi2 {
0078 pinctrl-names = "default";
0079 pinctrl-0 = <&pinctrl_ecspi2>;
0080 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
0081 status = "disabled";
0082 };
0083
0084 &eqos { /* First ethernet */
0085 pinctrl-names = "default";
0086 pinctrl-0 = <&pinctrl_eqos>;
0087 phy-handle = <ðphy0g>;
0088 phy-mode = "rgmii-id";
0089 status = "okay";
0090
0091 mdio {
0092 compatible = "snps,dwmac-mdio";
0093 #address-cells = <1>;
0094 #size-cells = <0>;
0095
0096 /* Up to one of these two PHYs may be populated. */
0097 ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
0098 compatible = "ethernet-phy-id0007.c110",
0099 "ethernet-phy-ieee802.3-c22";
0100 interrupt-parent = <&gpio3>;
0101 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
0102 pinctrl-0 = <&pinctrl_ethphy0>;
0103 pinctrl-names = "default";
0104 reg = <1>;
0105 reset-assert-us = <1000>;
0106 reset-deassert-us = <1000>;
0107 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
0108 /* Non-default PHY population option. */
0109 status = "disabled";
0110 };
0111
0112 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
0113 compatible = "ethernet-phy-id0022.1642",
0114 "ethernet-phy-ieee802.3-c22";
0115 interrupt-parent = <&gpio3>;
0116 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
0117 micrel,led-mode = <0>;
0118 pinctrl-0 = <&pinctrl_ethphy0>;
0119 pinctrl-names = "default";
0120 reg = <5>;
0121 reset-assert-us = <1000>;
0122 reset-deassert-us = <1000>;
0123 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
0124 /* Default PHY population option. */
0125 status = "okay";
0126 };
0127 };
0128 };
0129
0130 &fec { /* Second ethernet */
0131 pinctrl-names = "default";
0132 pinctrl-0 = <&pinctrl_fec>;
0133 phy-handle = <ðphy1f>;
0134 phy-mode = "rgmii";
0135 fsl,magic-packet;
0136 status = "okay";
0137
0138 mdio {
0139 #address-cells = <1>;
0140 #size-cells = <0>;
0141
0142 /* Up to one PHY may be populated. */
0143 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
0144 compatible = "ethernet-phy-id0007.c110",
0145 "ethernet-phy-ieee802.3-c22";
0146 interrupt-parent = <&gpio4>;
0147 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0148 pinctrl-0 = <&pinctrl_ethphy1>;
0149 pinctrl-names = "default";
0150 reg = <1>;
0151 reset-assert-us = <1000>;
0152 reset-deassert-us = <1000>;
0153 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
0154 /* Non-default PHY population option. */
0155 status = "disabled";
0156 };
0157 };
0158 };
0159
0160 &flexcan1 {
0161 pinctrl-names = "default";
0162 pinctrl-0 = <&pinctrl_flexcan1>;
0163 status = "disabled";
0164 };
0165
0166 &flexcan2 {
0167 pinctrl-names = "default";
0168 pinctrl-0 = <&pinctrl_flexcan2>;
0169 status = "disabled";
0170 };
0171
0172 &flexspi {
0173 pinctrl-names = "default";
0174 pinctrl-0 = <&pinctrl_flexspi>;
0175 status = "okay";
0176
0177 flash@0 { /* W25Q128JWPIM */
0178 compatible = "jedec,spi-nor";
0179 reg = <0>;
0180 spi-max-frequency = <80000000>;
0181 spi-tx-bus-width = <4>;
0182 spi-rx-bus-width = <4>;
0183 };
0184 };
0185
0186 &gpio1 {
0187 gpio-line-names =
0188 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
0189 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
0190 "", "", "", "", "", "", "", "",
0191 "", "", "", "", "", "", "", "";
0192 };
0193
0194 &gpio2 {
0195 gpio-line-names =
0196 "", "", "", "", "", "", "", "",
0197 "", "", "", "DHCOM-K", "", "", "", "",
0198 "", "", "", "", "DHCOM-INT", "", "", "",
0199 "", "", "", "", "", "", "", "";
0200 };
0201
0202 &gpio3 {
0203 gpio-line-names =
0204 "", "", "", "", "", "", "", "",
0205 "", "", "", "", "", "", "SOM-HW0", "",
0206 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
0207 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
0208 };
0209
0210 &gpio4 {
0211 gpio-line-names =
0212 "", "", "", "", "", "", "", "",
0213 "", "", "", "", "", "", "", "",
0214 "", "", "", "SOM-HW1", "", "", "", "",
0215 "", "", "", "DHCOM-D", "", "", "", "";
0216 };
0217
0218 &gpio5 {
0219 gpio-line-names =
0220 "", "", "DHCOM-C", "", "", "", "", "",
0221 "", "", "", "", "", "", "", "",
0222 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
0223 "", "", "", "", "", "", "", "";
0224 };
0225
0226 &i2c3 {
0227 clock-frequency = <100000>;
0228 pinctrl-names = "default", "gpio";
0229 pinctrl-0 = <&pinctrl_i2c3>;
0230 pinctrl-1 = <&pinctrl_i2c3_gpio>;
0231 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0232 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0233 status = "okay";
0234
0235 pmic: pmic@25 {
0236 compatible = "nxp,pca9450c";
0237 reg = <0x25>;
0238 pinctrl-names = "default";
0239 pinctrl-0 = <&pinctrl_pmic>;
0240 interrupt-parent = <&gpio1>;
0241 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0242 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
0243
0244 /*
0245 * i.MX 8M Plus Data Sheet for Consumer Products
0246 * 3.1.4 Operating ranges
0247 * MIMX8ML8CVNKZAB
0248 */
0249 regulators {
0250 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
0251 regulator-compatible = "BUCK1";
0252 regulator-min-microvolt = <850000>;
0253 regulator-max-microvolt = <1000000>;
0254 regulator-ramp-delay = <3125>;
0255 regulator-always-on;
0256 regulator-boot-on;
0257 };
0258
0259 buck2: BUCK2 { /* VDD_ARM */
0260 regulator-compatible = "BUCK2";
0261 regulator-min-microvolt = <850000>;
0262 regulator-max-microvolt = <1000000>;
0263 regulator-ramp-delay = <3125>;
0264 regulator-always-on;
0265 regulator-boot-on;
0266 };
0267
0268 buck4: BUCK4 { /* VDD_3V3 */
0269 regulator-compatible = "BUCK4";
0270 regulator-min-microvolt = <3300000>;
0271 regulator-max-microvolt = <3300000>;
0272 regulator-always-on;
0273 regulator-boot-on;
0274 };
0275
0276 buck5: BUCK5 { /* VDD_1V8 */
0277 regulator-compatible = "BUCK5";
0278 regulator-min-microvolt = <1800000>;
0279 regulator-max-microvolt = <1800000>;
0280 regulator-always-on;
0281 regulator-boot-on;
0282 };
0283
0284 buck6: BUCK6 { /* NVCC_DRAM_1V1 */
0285 regulator-compatible = "BUCK6";
0286 regulator-min-microvolt = <1100000>;
0287 regulator-max-microvolt = <1100000>;
0288 regulator-always-on;
0289 regulator-boot-on;
0290 };
0291
0292 ldo1: LDO1 { /* NVCC_SNVS_1V8 */
0293 regulator-compatible = "LDO1";
0294 regulator-min-microvolt = <1800000>;
0295 regulator-max-microvolt = <1800000>;
0296 regulator-always-on;
0297 regulator-boot-on;
0298 };
0299
0300 ldo3: LDO3 { /* VDDA_1V8 */
0301 regulator-compatible = "LDO3";
0302 regulator-min-microvolt = <1800000>;
0303 regulator-max-microvolt = <1800000>;
0304 regulator-always-on;
0305 regulator-boot-on;
0306 };
0307
0308 ldo4: LDO4 { /* PMIC_LDO4 */
0309 regulator-compatible = "LDO4";
0310 regulator-min-microvolt = <3300000>;
0311 regulator-max-microvolt = <3300000>;
0312 };
0313
0314 ldo5: LDO5 { /* NVCC_SD2 */
0315 regulator-compatible = "LDO5";
0316 regulator-min-microvolt = <1800000>;
0317 regulator-max-microvolt = <3300000>;
0318 };
0319 };
0320 };
0321
0322 adc@48 {
0323 compatible = "ti,tla2024";
0324 reg = <0x48>;
0325 #address-cells = <1>;
0326 #size-cells = <0>;
0327
0328 channel@0 { /* Voltage over AIN0 and AIN1. */
0329 reg = <0>;
0330 };
0331
0332 channel@1 { /* Voltage over AIN0 and AIN3. */
0333 reg = <1>;
0334 };
0335
0336 channel@2 { /* Voltage over AIN1 and AIN3. */
0337 reg = <2>;
0338 };
0339
0340 channel@3 { /* Voltage over AIN2 and AIN3. */
0341 reg = <3>;
0342 };
0343
0344 channel@4 { /* Voltage over AIN0 and GND. */
0345 reg = <4>;
0346 };
0347
0348 channel@5 { /* Voltage over AIN1 and GND. */
0349 reg = <5>;
0350 };
0351
0352 channel@6 { /* Voltage over AIN2 and GND. */
0353 reg = <6>;
0354 };
0355
0356 channel@7 { /* Voltage over AIN3 and GND. */
0357 reg = <7>;
0358 };
0359 };
0360
0361 touchscreen@49 {
0362 compatible = "ti,tsc2004";
0363 reg = <0x49>;
0364 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
0365 pinctrl-names = "default";
0366 pinctrl-0 = <&pinctrl_touch>;
0367 vio-supply = <&buck4>;
0368 };
0369
0370 eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */
0371 compatible = "atmel,24c02";
0372 pagesize = <16>;
0373 reg = <0x50>;
0374 };
0375
0376 rv3032: rtc@51 {
0377 compatible = "microcrystal,rv3032";
0378 reg = <0x51>;
0379 interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
0380 pinctrl-names = "default";
0381 pinctrl-0 = <&pinctrl_rtc>;
0382 };
0383
0384 eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */
0385 compatible = "atmel,24c02";
0386 pagesize = <16>;
0387 reg = <0x53>;
0388 };
0389 };
0390
0391 &i2c4 {
0392 clock-frequency = <100000>;
0393 pinctrl-names = "default", "gpio";
0394 pinctrl-0 = <&pinctrl_i2c4>;
0395 pinctrl-1 = <&pinctrl_i2c4_gpio>;
0396 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0397 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0398 status = "okay";
0399 };
0400
0401 &i2c5 { /* HDMI EDID bus */
0402 clock-frequency = <100000>;
0403 pinctrl-names = "default", "gpio";
0404 pinctrl-0 = <&pinctrl_i2c5>;
0405 pinctrl-1 = <&pinctrl_i2c5_gpio>;
0406 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0407 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0408 status = "okay";
0409 };
0410
0411 &pwm1 {
0412 pinctrl-0 = <&pinctrl_pwm1>;
0413 pinctrl-names = "default";
0414 status = "disabled";
0415 };
0416
0417 &uart1 {
0418 /* CA53 console */
0419 pinctrl-names = "default";
0420 pinctrl-0 = <&pinctrl_uart1>;
0421 status = "okay";
0422 };
0423
0424 &uart2 {
0425 /* Bluetooth */
0426 pinctrl-names = "default";
0427 pinctrl-0 = <&pinctrl_uart2>;
0428 uart-has-rtscts;
0429 status = "okay";
0430 };
0431
0432 &uart3 {
0433 pinctrl-names = "default";
0434 pinctrl-0 = <&pinctrl_uart3>;
0435 uart-has-rtscts;
0436 status = "okay";
0437 };
0438
0439 &uart4 {
0440 pinctrl-names = "default";
0441 pinctrl-0 = <&pinctrl_uart4>;
0442 status = "okay";
0443 };
0444
0445 &usb3_phy0 {
0446 status = "okay";
0447 };
0448
0449 &usb3_0 {
0450 status = "okay";
0451 };
0452
0453 &usb_dwc3_0 {
0454 pinctrl-names = "default";
0455 pinctrl-0 = <&pinctrl_usb0_vbus>;
0456 dr_mode = "otg";
0457 status = "okay";
0458 };
0459
0460 &usb3_phy1 {
0461 status = "okay";
0462 };
0463
0464 &usb3_1 {
0465 status = "okay";
0466 };
0467
0468 &usb_dwc3_1 {
0469 pinctrl-names = "default";
0470 pinctrl-0 = <&pinctrl_usb1_vbus>;
0471 dr_mode = "host";
0472 status = "okay";
0473 };
0474
0475 /* SDIO WiFi */
0476 &usdhc1 {
0477 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0478 pinctrl-0 = <&pinctrl_usdhc1>;
0479 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0480 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0481 vmmc-supply = <&buck4>;
0482 bus-width = <4>;
0483 non-removable;
0484 cap-power-off-card;
0485 keep-power-in-suspend;
0486 status = "okay";
0487
0488 #address-cells = <1>;
0489 #size-cells = <0>;
0490
0491 brcmf: bcrmf@1 { /* muRata 2AE */
0492 reg = <1>;
0493 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
0494 /*
0495 * The "host-wake" interrupt output is by default not
0496 * connected to the SoC, but can be connected on to
0497 * SoC pin on the carrier board.
0498 */
0499 reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
0500 };
0501 };
0502
0503 /* SD slot */
0504 &usdhc2 {
0505 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0506 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0507 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0508 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0509 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
0510 vmmc-supply = <®_usdhc2_vmmc>;
0511 bus-width = <4>;
0512 status = "okay";
0513 };
0514
0515 /* eMMC */
0516 &usdhc3 {
0517 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0518 pinctrl-0 = <&pinctrl_usdhc3>;
0519 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0520 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0521 vmmc-supply = <&buck4>;
0522 vqmmc-supply = <&buck5>;
0523 bus-width = <8>;
0524 non-removable;
0525 status = "okay";
0526 };
0527
0528 &wdog1 {
0529 pinctrl-names = "default";
0530 pinctrl-0 = <&pinctrl_wdog>;
0531 fsl,ext-reset-output;
0532 status = "okay";
0533 };
0534
0535 &iomuxc {
0536 pinctrl-0 = <&pinctrl_hog_base
0537 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
0538 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
0539 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
0540 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
0541 /* GPIO_M is connected to CLKOUT2 */
0542 &pinctrl_dhcom_int>;
0543 pinctrl-names = "default";
0544
0545 pinctrl_dhcom_a: dhcom-a-grp {
0546 fsl,pins = <
0547 /* ENET_QOS_EVENT0-OUT */
0548 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2
0549 >;
0550 };
0551
0552 pinctrl_dhcom_b: dhcom-b-grp {
0553 fsl,pins = <
0554 /* ENET_QOS_EVENT0-IN */
0555 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2
0556 >;
0557 };
0558
0559 pinctrl_dhcom_c: dhcom-c-grp {
0560 fsl,pins = <
0561 /* GPIO_C */
0562 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2
0563 >;
0564 };
0565
0566 pinctrl_dhcom_d: dhcom-d-grp {
0567 fsl,pins = <
0568 /* GPIO_D */
0569 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2
0570 >;
0571 };
0572
0573 pinctrl_dhcom_e: dhcom-e-grp {
0574 fsl,pins = <
0575 /* GPIO_E */
0576 MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2
0577 >;
0578 };
0579
0580 pinctrl_dhcom_f: dhcom-f-grp {
0581 fsl,pins = <
0582 /* GPIO_F */
0583 MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2
0584 >;
0585 };
0586
0587 pinctrl_dhcom_g: dhcom-g-grp {
0588 fsl,pins = <
0589 /* GPIO_G */
0590 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2
0591 >;
0592 };
0593
0594 pinctrl_dhcom_h: dhcom-h-grp {
0595 fsl,pins = <
0596 /* GPIO_H */
0597 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2
0598 >;
0599 };
0600
0601 pinctrl_dhcom_i: dhcom-i-grp {
0602 fsl,pins = <
0603 /* CSI1_SYNC */
0604 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
0605 >;
0606 };
0607
0608 pinctrl_dhcom_j: dhcom-j-grp {
0609 fsl,pins = <
0610 /* CSIx_#RST */
0611 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2
0612 >;
0613 };
0614
0615 pinctrl_dhcom_k: dhcom-k-grp {
0616 fsl,pins = <
0617 /* CSIx_PWDN */
0618 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2
0619 >;
0620 };
0621
0622 pinctrl_dhcom_l: dhcom-l-grp {
0623 fsl,pins = <
0624 /* CSI2_SYNC */
0625 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2
0626 >;
0627 };
0628
0629 pinctrl_dhcom_int: dhcom-int-grp {
0630 fsl,pins = <
0631 /* INT_HIGHEST_PRIO */
0632 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2
0633 >;
0634 };
0635
0636 pinctrl_hog_base: dhcom-hog-base-grp {
0637 fsl,pins = <
0638 /* GPIOs for memory coding */
0639 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080
0640 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080
0641 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080
0642 /* GPIOs for hardware coding */
0643 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080
0644 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080
0645 MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080
0646 >;
0647 };
0648
0649 pinctrl_ecspi1: dhcom-ecspi1-grp {
0650 fsl,pins = <
0651 MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x44
0652 MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x44
0653 MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x44
0654 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x40
0655 >;
0656 };
0657
0658 pinctrl_ecspi2: dhcom-ecspi2-grp {
0659 fsl,pins = <
0660 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
0661 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
0662 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
0663 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
0664 >;
0665 };
0666
0667 pinctrl_eqos: dhcom-eqos-grp { /* RGMII */
0668 fsl,pins = <
0669 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
0670 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
0671 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
0672 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
0673 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
0674 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
0675 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
0676 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
0677 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
0678 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
0679 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
0680 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
0681 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
0682 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
0683 >;
0684 };
0685
0686 pinctrl_enet_vio: dhcom-enet-vio-grp {
0687 fsl,pins = <
0688 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
0689 >;
0690 };
0691
0692 pinctrl_ethphy0: dhcom-ethphy0-grp {
0693 fsl,pins = <
0694 /* ENET1_#RST Reset */
0695 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
0696 /* ENET1_#INT Interrupt */
0697 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22
0698 >;
0699 };
0700
0701 pinctrl_ethphy1: dhcom-ethphy1-grp {
0702 fsl,pins = <
0703 /* ENET1_#RST Reset */
0704 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11
0705 /* ENET1_#INT Interrupt */
0706 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11
0707 >;
0708 };
0709
0710 pinctrl_fec: dhcom-fec-grp {
0711 fsl,pins = <
0712 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f
0713 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
0714 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
0715 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
0716 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
0717 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
0718 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
0719 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
0720 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
0721 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
0722 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
0723 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
0724 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
0725 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
0726 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
0727 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f
0728 >;
0729 };
0730
0731 pinctrl_flexcan1: dhcom-flexcan1-grp {
0732 fsl,pins = <
0733 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
0734 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
0735 >;
0736 };
0737
0738 pinctrl_flexcan2: dhcom-flexcan2-grp {
0739 fsl,pins = <
0740 MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154
0741 MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154
0742 >;
0743 };
0744
0745 pinctrl_flexspi: dhcom-flexspi-grp {
0746 fsl,pins = <
0747 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
0748 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
0749 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
0750 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
0751 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
0752 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
0753 >;
0754 };
0755
0756 pinctrl_hdmi: dhcom-hdmi-grp {
0757 fsl,pins = <
0758 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154
0759 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154
0760 >;
0761 };
0762
0763 pinctrl_i2c3: dhcom-i2c3-grp {
0764 fsl,pins = <
0765 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084
0766 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084
0767 >;
0768 };
0769
0770 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
0771 fsl,pins = <
0772 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84
0773 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84
0774 >;
0775 };
0776
0777 pinctrl_i2c4: dhcom-i2c4-grp {
0778 fsl,pins = <
0779 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084
0780 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084
0781 >;
0782 };
0783
0784 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
0785 fsl,pins = <
0786 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84
0787 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84
0788 >;
0789 };
0790
0791 pinctrl_i2c5: dhcom-i2c5-grp {
0792 fsl,pins = <
0793 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084
0794 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084
0795 >;
0796 };
0797
0798 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
0799 fsl,pins = <
0800 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84
0801 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84
0802 >;
0803 };
0804
0805 pinctrl_pmic: dhcom-pmic-grp {
0806 fsl,pins = <
0807 /* PMIC_nINT */
0808 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
0809 >;
0810 };
0811
0812 pinctrl_pwm1: dhcom-pwm1-grp {
0813 fsl,pins = <
0814 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6
0815 >;
0816 };
0817
0818 pinctrl_rtc: dhcom-rtc-grp {
0819 fsl,pins = <
0820 /* RTC_#INT Interrupt */
0821 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080
0822 >;
0823 };
0824
0825 pinctrl_touch: dhcom-touch-grp {
0826 fsl,pins = <
0827 /* #TOUCH_INT */
0828 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080
0829 >;
0830 };
0831
0832 pinctrl_uart1: dhcom-uart1-grp {
0833 fsl,pins = <
0834 /* Console UART */
0835 MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49
0836 MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49
0837 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49
0838 MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49
0839 >;
0840 };
0841
0842 pinctrl_uart2: dhcom-uart2-grp {
0843 fsl,pins = <
0844 /* Bluetooth UART */
0845 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
0846 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
0847 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49
0848 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
0849 >;
0850 };
0851
0852 pinctrl_uart3: dhcom-uart3-grp {
0853 fsl,pins = <
0854 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49
0855 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49
0856 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49
0857 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49
0858 >;
0859 };
0860
0861 pinctrl_uart4: dhcom-uart4-grp {
0862 fsl,pins = <
0863 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
0864 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
0865 >;
0866 };
0867
0868 pinctrl_usb0_vbus: dhcom-usb0-grp {
0869 fsl,pins = <
0870 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
0871 >;
0872 };
0873
0874 pinctrl_usb1_vbus: dhcom-usb1-grp {
0875 fsl,pins = <
0876 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6
0877 MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80
0878 >;
0879 };
0880
0881 pinctrl_usdhc1: dhcom-usdhc1-grp {
0882 fsl,pins = <
0883 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
0884 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
0885 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
0886 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
0887 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
0888 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
0889 /* BT_REG_EN */
0890 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
0891 /* WL_REG_EN */
0892 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
0893 >;
0894 };
0895
0896 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
0897 fsl,pins = <
0898 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
0899 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
0900 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
0901 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
0902 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
0903 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
0904 /* BT_REG_EN */
0905 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
0906 /* WL_REG_EN */
0907 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
0908 >;
0909 };
0910
0911 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
0912 fsl,pins = <
0913 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
0914 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
0915 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
0916 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
0917 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
0918 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
0919 /* BT_REG_EN */
0920 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
0921 /* WL_REG_EN */
0922 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
0923 >;
0924 };
0925
0926 pinctrl_usdhc2: dhcom-usdhc2-grp {
0927 fsl,pins = <
0928 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
0929 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
0930 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
0931 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
0932 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
0933 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
0934 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
0935 >;
0936 };
0937
0938 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
0939 fsl,pins = <
0940 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
0941 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
0942 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
0943 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
0944 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
0945 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
0946 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
0947 >;
0948 };
0949
0950 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
0951 fsl,pins = <
0952 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
0953 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
0954 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
0955 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
0956 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
0957 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
0958 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
0959 >;
0960 };
0961
0962 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
0963 fsl,pins = <
0964 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20
0965 >;
0966 };
0967
0968 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
0969 fsl,pins = <
0970 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080
0971 >;
0972 };
0973
0974 pinctrl_usdhc3: dhcom-usdhc3-grp {
0975 fsl,pins = <
0976 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
0977 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
0978 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
0979 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
0980 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
0981 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
0982 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
0983 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
0984 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
0985 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
0986 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
0987 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
0988 >;
0989 };
0990
0991 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
0992 fsl,pins = <
0993 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
0994 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
0995 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
0996 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
0997 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
0998 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
0999 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1000 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1001 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1002 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1003 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1004 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1005 >;
1006 };
1007
1008 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1009 fsl,pins = <
1010 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1011 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1012 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1013 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1014 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1015 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1016 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1017 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1018 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1019 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1020 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1021 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1022 >;
1023 };
1024
1025 pinctrl_wdog: dhcom-wdog-grp {
1026 fsl,pins = <
1027 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
1028 >;
1029 };
1030 };
