0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2019 NXP
0004 */
0005
0006 #include <dt-bindings/clock/imx8mn-clock.h>
0007 #include <dt-bindings/power/imx8mn-power.h>
0008 #include <dt-bindings/reset/imx8mq-reset.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/input/input.h>
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/thermal/thermal.h>
0013
0014 #include "imx8mn-pinfunc.h"
0015
0016 / {
0017 interrupt-parent = <&gic>;
0018 #address-cells = <2>;
0019 #size-cells = <2>;
0020
0021 aliases {
0022 ethernet0 = &fec1;
0023 gpio0 = &gpio1;
0024 gpio1 = &gpio2;
0025 gpio2 = &gpio3;
0026 gpio3 = &gpio4;
0027 gpio4 = &gpio5;
0028 i2c0 = &i2c1;
0029 i2c1 = &i2c2;
0030 i2c2 = &i2c3;
0031 i2c3 = &i2c4;
0032 mmc0 = &usdhc1;
0033 mmc1 = &usdhc2;
0034 mmc2 = &usdhc3;
0035 serial0 = &uart1;
0036 serial1 = &uart2;
0037 serial2 = &uart3;
0038 serial3 = &uart4;
0039 spi0 = &ecspi1;
0040 spi1 = &ecspi2;
0041 spi2 = &ecspi3;
0042 };
0043
0044 cpus {
0045 #address-cells = <1>;
0046 #size-cells = <0>;
0047
0048 idle-states {
0049 entry-method = "psci";
0050
0051 cpu_pd_wait: cpu-pd-wait {
0052 compatible = "arm,idle-state";
0053 arm,psci-suspend-param = <0x0010033>;
0054 local-timer-stop;
0055 entry-latency-us = <1000>;
0056 exit-latency-us = <700>;
0057 min-residency-us = <2700>;
0058 };
0059 };
0060
0061 A53_0: cpu@0 {
0062 device_type = "cpu";
0063 compatible = "arm,cortex-a53";
0064 reg = <0x0>;
0065 clock-latency = <61036>;
0066 clocks = <&clk IMX8MN_CLK_ARM>;
0067 enable-method = "psci";
0068 i-cache-size = <0x8000>;
0069 i-cache-line-size = <64>;
0070 i-cache-sets = <256>;
0071 d-cache-size = <0x8000>;
0072 d-cache-line-size = <64>;
0073 d-cache-sets = <128>;
0074 next-level-cache = <&A53_L2>;
0075 operating-points-v2 = <&a53_opp_table>;
0076 nvmem-cells = <&cpu_speed_grade>;
0077 nvmem-cell-names = "speed_grade";
0078 cpu-idle-states = <&cpu_pd_wait>;
0079 #cooling-cells = <2>;
0080 };
0081
0082 A53_1: cpu@1 {
0083 device_type = "cpu";
0084 compatible = "arm,cortex-a53";
0085 reg = <0x1>;
0086 clock-latency = <61036>;
0087 clocks = <&clk IMX8MN_CLK_ARM>;
0088 enable-method = "psci";
0089 i-cache-size = <0x8000>;
0090 i-cache-line-size = <64>;
0091 i-cache-sets = <256>;
0092 d-cache-size = <0x8000>;
0093 d-cache-line-size = <64>;
0094 d-cache-sets = <128>;
0095 next-level-cache = <&A53_L2>;
0096 operating-points-v2 = <&a53_opp_table>;
0097 cpu-idle-states = <&cpu_pd_wait>;
0098 #cooling-cells = <2>;
0099 };
0100
0101 A53_2: cpu@2 {
0102 device_type = "cpu";
0103 compatible = "arm,cortex-a53";
0104 reg = <0x2>;
0105 clock-latency = <61036>;
0106 clocks = <&clk IMX8MN_CLK_ARM>;
0107 enable-method = "psci";
0108 i-cache-size = <0x8000>;
0109 i-cache-line-size = <64>;
0110 i-cache-sets = <256>;
0111 d-cache-size = <0x8000>;
0112 d-cache-line-size = <64>;
0113 d-cache-sets = <128>;
0114 next-level-cache = <&A53_L2>;
0115 operating-points-v2 = <&a53_opp_table>;
0116 cpu-idle-states = <&cpu_pd_wait>;
0117 #cooling-cells = <2>;
0118 };
0119
0120 A53_3: cpu@3 {
0121 device_type = "cpu";
0122 compatible = "arm,cortex-a53";
0123 reg = <0x3>;
0124 clock-latency = <61036>;
0125 clocks = <&clk IMX8MN_CLK_ARM>;
0126 enable-method = "psci";
0127 i-cache-size = <0x8000>;
0128 i-cache-line-size = <64>;
0129 i-cache-sets = <256>;
0130 d-cache-size = <0x8000>;
0131 d-cache-line-size = <64>;
0132 d-cache-sets = <128>;
0133 next-level-cache = <&A53_L2>;
0134 operating-points-v2 = <&a53_opp_table>;
0135 cpu-idle-states = <&cpu_pd_wait>;
0136 #cooling-cells = <2>;
0137 };
0138
0139 A53_L2: l2-cache0 {
0140 compatible = "cache";
0141 cache-level = <2>;
0142 cache-size = <0x80000>;
0143 cache-line-size = <64>;
0144 cache-sets = <512>;
0145 };
0146 };
0147
0148 a53_opp_table: opp-table {
0149 compatible = "operating-points-v2";
0150 opp-shared;
0151
0152 opp-1200000000 {
0153 opp-hz = /bits/ 64 <1200000000>;
0154 opp-microvolt = <850000>;
0155 opp-supported-hw = <0xb00>, <0x7>;
0156 clock-latency-ns = <150000>;
0157 opp-suspend;
0158 };
0159
0160 opp-1400000000 {
0161 opp-hz = /bits/ 64 <1400000000>;
0162 opp-microvolt = <950000>;
0163 opp-supported-hw = <0x300>, <0x7>;
0164 clock-latency-ns = <150000>;
0165 opp-suspend;
0166 };
0167
0168 opp-1500000000 {
0169 opp-hz = /bits/ 64 <1500000000>;
0170 opp-microvolt = <1000000>;
0171 opp-supported-hw = <0x100>, <0x3>;
0172 clock-latency-ns = <150000>;
0173 opp-suspend;
0174 };
0175 };
0176
0177 osc_32k: clock-osc-32k {
0178 compatible = "fixed-clock";
0179 #clock-cells = <0>;
0180 clock-frequency = <32768>;
0181 clock-output-names = "osc_32k";
0182 };
0183
0184 osc_24m: clock-osc-24m {
0185 compatible = "fixed-clock";
0186 #clock-cells = <0>;
0187 clock-frequency = <24000000>;
0188 clock-output-names = "osc_24m";
0189 };
0190
0191 clk_ext1: clock-ext1 {
0192 compatible = "fixed-clock";
0193 #clock-cells = <0>;
0194 clock-frequency = <133000000>;
0195 clock-output-names = "clk_ext1";
0196 };
0197
0198 clk_ext2: clock-ext2 {
0199 compatible = "fixed-clock";
0200 #clock-cells = <0>;
0201 clock-frequency = <133000000>;
0202 clock-output-names = "clk_ext2";
0203 };
0204
0205 clk_ext3: clock-ext3 {
0206 compatible = "fixed-clock";
0207 #clock-cells = <0>;
0208 clock-frequency = <133000000>;
0209 clock-output-names = "clk_ext3";
0210 };
0211
0212 clk_ext4: clock-ext4 {
0213 compatible = "fixed-clock";
0214 #clock-cells = <0>;
0215 clock-frequency = <133000000>;
0216 clock-output-names = "clk_ext4";
0217 };
0218
0219 pmu {
0220 compatible = "arm,cortex-a53-pmu";
0221 interrupts = <GIC_PPI 7
0222 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0223 };
0224
0225 psci {
0226 compatible = "arm,psci-1.0";
0227 method = "smc";
0228 };
0229
0230 thermal-zones {
0231 cpu-thermal {
0232 polling-delay-passive = <250>;
0233 polling-delay = <2000>;
0234 thermal-sensors = <&tmu>;
0235 trips {
0236 cpu_alert0: trip0 {
0237 temperature = <85000>;
0238 hysteresis = <2000>;
0239 type = "passive";
0240 };
0241
0242 cpu_crit0: trip1 {
0243 temperature = <95000>;
0244 hysteresis = <2000>;
0245 type = "critical";
0246 };
0247 };
0248
0249 cooling-maps {
0250 map0 {
0251 trip = <&cpu_alert0>;
0252 cooling-device =
0253 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0254 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0255 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0256 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0257 };
0258 };
0259 };
0260 };
0261
0262 timer {
0263 compatible = "arm,armv8-timer";
0264 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0265 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0266 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0267 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0268 clock-frequency = <8000000>;
0269 arm,no-tick-in-suspend;
0270 };
0271
0272 soc: soc@0 {
0273 compatible = "fsl,imx8mn-soc", "simple-bus";
0274 #address-cells = <1>;
0275 #size-cells = <1>;
0276 ranges = <0x0 0x0 0x0 0x3e000000>;
0277 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
0278 nvmem-cells = <&imx8mn_uid>;
0279 nvmem-cell-names = "soc_unique_id";
0280
0281 aips1: bus@30000000 {
0282 compatible = "fsl,aips-bus", "simple-bus";
0283 reg = <0x30000000 0x400000>;
0284 #address-cells = <1>;
0285 #size-cells = <1>;
0286 ranges;
0287
0288 spba2: spba-bus@30000000 {
0289 compatible = "fsl,spba-bus", "simple-bus";
0290 #address-cells = <1>;
0291 #size-cells = <1>;
0292 reg = <0x30000000 0x100000>;
0293 ranges;
0294
0295 sai2: sai@30020000 {
0296 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
0297 reg = <0x30020000 0x10000>;
0298 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0299 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
0300 <&clk IMX8MN_CLK_DUMMY>,
0301 <&clk IMX8MN_CLK_SAI2_ROOT>,
0302 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
0303 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
0304 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
0305 dma-names = "rx", "tx";
0306 status = "disabled";
0307 };
0308
0309 sai3: sai@30030000 {
0310 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
0311 reg = <0x30030000 0x10000>;
0312 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0313 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
0314 <&clk IMX8MN_CLK_DUMMY>,
0315 <&clk IMX8MN_CLK_SAI3_ROOT>,
0316 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
0317 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
0318 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
0319 dma-names = "rx", "tx";
0320 status = "disabled";
0321 };
0322
0323 sai5: sai@30050000 {
0324 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
0325 reg = <0x30050000 0x10000>;
0326 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0327 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
0328 <&clk IMX8MN_CLK_DUMMY>,
0329 <&clk IMX8MN_CLK_SAI5_ROOT>,
0330 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
0331 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
0332 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
0333 dma-names = "rx", "tx";
0334 fsl,shared-interrupt;
0335 fsl,dataline = <0 0xf 0xf>;
0336 status = "disabled";
0337 };
0338
0339 sai6: sai@30060000 {
0340 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
0341 reg = <0x30060000 0x10000>;
0342 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0343 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
0344 <&clk IMX8MN_CLK_DUMMY>,
0345 <&clk IMX8MN_CLK_SAI6_ROOT>,
0346 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
0347 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
0348 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
0349 dma-names = "rx", "tx";
0350 status = "disabled";
0351 };
0352
0353 micfil: audio-controller@30080000 {
0354 compatible = "fsl,imx8mm-micfil";
0355 reg = <0x30080000 0x10000>;
0356 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0357 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0358 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
0359 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0360 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
0361 <&clk IMX8MN_CLK_PDM_ROOT>,
0362 <&clk IMX8MN_AUDIO_PLL1_OUT>,
0363 <&clk IMX8MN_AUDIO_PLL2_OUT>,
0364 <&clk IMX8MN_CLK_EXT3>;
0365 clock-names = "ipg_clk", "ipg_clk_app",
0366 "pll8k", "pll11k", "clkext3";
0367 dmas = <&sdma2 24 25 0x80000000>;
0368 dma-names = "rx";
0369 status = "disabled";
0370 };
0371
0372 spdif1: spdif@30090000 {
0373 compatible = "fsl,imx35-spdif";
0374 reg = <0x30090000 0x10000>;
0375 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0376 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
0377 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
0378 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
0379 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
0380 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
0381 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
0382 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
0383 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
0384 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
0385 <&clk IMX8MN_CLK_DUMMY>; /* spba */
0386 clock-names = "core", "rxtx0",
0387 "rxtx1", "rxtx2",
0388 "rxtx3", "rxtx4",
0389 "rxtx5", "rxtx6",
0390 "rxtx7", "spba";
0391 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
0392 dma-names = "rx", "tx";
0393 status = "disabled";
0394 };
0395
0396 sai7: sai@300b0000 {
0397 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
0398 reg = <0x300b0000 0x10000>;
0399 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0400 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
0401 <&clk IMX8MN_CLK_DUMMY>,
0402 <&clk IMX8MN_CLK_SAI7_ROOT>,
0403 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
0404 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
0405 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
0406 dma-names = "rx", "tx";
0407 status = "disabled";
0408 };
0409
0410 easrc: easrc@300c0000 {
0411 compatible = "fsl,imx8mn-easrc";
0412 reg = <0x300c0000 0x10000>;
0413 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0414 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
0415 clock-names = "mem";
0416 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
0417 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
0418 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
0419 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
0420 dma-names = "ctx0_rx", "ctx0_tx",
0421 "ctx1_rx", "ctx1_tx",
0422 "ctx2_rx", "ctx2_tx",
0423 "ctx3_rx", "ctx3_tx";
0424 firmware-name = "imx/easrc/easrc-imx8mn.bin";
0425 fsl,asrc-rate = <8000>;
0426 fsl,asrc-format = <2>;
0427 status = "disabled";
0428 };
0429 };
0430
0431 gpio1: gpio@30200000 {
0432 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
0433 reg = <0x30200000 0x10000>;
0434 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
0435 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0436 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
0437 gpio-controller;
0438 #gpio-cells = <2>;
0439 interrupt-controller;
0440 #interrupt-cells = <2>;
0441 gpio-ranges = <&iomuxc 0 10 30>;
0442 };
0443
0444 gpio2: gpio@30210000 {
0445 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
0446 reg = <0x30210000 0x10000>;
0447 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
0448 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0449 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
0450 gpio-controller;
0451 #gpio-cells = <2>;
0452 interrupt-controller;
0453 #interrupt-cells = <2>;
0454 gpio-ranges = <&iomuxc 0 40 21>;
0455 };
0456
0457 gpio3: gpio@30220000 {
0458 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
0459 reg = <0x30220000 0x10000>;
0460 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
0461 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0462 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
0463 gpio-controller;
0464 #gpio-cells = <2>;
0465 interrupt-controller;
0466 #interrupt-cells = <2>;
0467 gpio-ranges = <&iomuxc 0 61 26>;
0468 };
0469
0470 gpio4: gpio@30230000 {
0471 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
0472 reg = <0x30230000 0x10000>;
0473 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0474 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0475 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
0476 gpio-controller;
0477 #gpio-cells = <2>;
0478 interrupt-controller;
0479 #interrupt-cells = <2>;
0480 gpio-ranges = <&iomuxc 21 108 11>;
0481 };
0482
0483 gpio5: gpio@30240000 {
0484 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
0485 reg = <0x30240000 0x10000>;
0486 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0487 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0488 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
0489 gpio-controller;
0490 #gpio-cells = <2>;
0491 interrupt-controller;
0492 #interrupt-cells = <2>;
0493 gpio-ranges = <&iomuxc 0 119 30>;
0494 };
0495
0496 tmu: tmu@30260000 {
0497 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
0498 reg = <0x30260000 0x10000>;
0499 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
0500 #thermal-sensor-cells = <0>;
0501 };
0502
0503 wdog1: watchdog@30280000 {
0504 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
0505 reg = <0x30280000 0x10000>;
0506 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0507 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
0508 status = "disabled";
0509 };
0510
0511 wdog2: watchdog@30290000 {
0512 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
0513 reg = <0x30290000 0x10000>;
0514 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0515 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
0516 status = "disabled";
0517 };
0518
0519 wdog3: watchdog@302a0000 {
0520 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
0521 reg = <0x302a0000 0x10000>;
0522 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0523 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
0524 status = "disabled";
0525 };
0526
0527 sdma3: dma-controller@302b0000 {
0528 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
0529 reg = <0x302b0000 0x10000>;
0530 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0531 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
0532 <&clk IMX8MN_CLK_SDMA3_ROOT>;
0533 clock-names = "ipg", "ahb";
0534 #dma-cells = <3>;
0535 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
0536 };
0537
0538 sdma2: dma-controller@302c0000 {
0539 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
0540 reg = <0x302c0000 0x10000>;
0541 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0542 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
0543 <&clk IMX8MN_CLK_SDMA2_ROOT>;
0544 clock-names = "ipg", "ahb";
0545 #dma-cells = <3>;
0546 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
0547 };
0548
0549 iomuxc: pinctrl@30330000 {
0550 compatible = "fsl,imx8mn-iomuxc";
0551 reg = <0x30330000 0x10000>;
0552 };
0553
0554 gpr: iomuxc-gpr@30340000 {
0555 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
0556 reg = <0x30340000 0x10000>;
0557 };
0558
0559 ocotp: efuse@30350000 {
0560 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
0561 reg = <0x30350000 0x10000>;
0562 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
0563 #address-cells = <1>;
0564 #size-cells = <1>;
0565
0566 imx8mn_uid: unique-id@410 {
0567 reg = <0x4 0x8>;
0568 };
0569
0570 cpu_speed_grade: speed-grade@10 {
0571 reg = <0x10 4>;
0572 };
0573
0574 fec_mac_address: mac-address@90 {
0575 reg = <0x90 6>;
0576 };
0577 };
0578
0579 anatop: anatop@30360000 {
0580 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
0581 "syscon";
0582 reg = <0x30360000 0x10000>;
0583 };
0584
0585 snvs: snvs@30370000 {
0586 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
0587 reg = <0x30370000 0x10000>;
0588
0589 snvs_rtc: snvs-rtc-lp {
0590 compatible = "fsl,sec-v4.0-mon-rtc-lp";
0591 regmap = <&snvs>;
0592 offset = <0x34>;
0593 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0594 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0595 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
0596 clock-names = "snvs-rtc";
0597 };
0598
0599 snvs_pwrkey: snvs-powerkey {
0600 compatible = "fsl,sec-v4.0-pwrkey";
0601 regmap = <&snvs>;
0602 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0603 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
0604 clock-names = "snvs-pwrkey";
0605 linux,keycode = <KEY_POWER>;
0606 wakeup-source;
0607 status = "disabled";
0608 };
0609 };
0610
0611 clk: clock-controller@30380000 {
0612 compatible = "fsl,imx8mn-ccm";
0613 reg = <0x30380000 0x10000>;
0614 #clock-cells = <1>;
0615 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
0616 <&clk_ext3>, <&clk_ext4>;
0617 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
0618 "clk_ext3", "clk_ext4";
0619 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
0620 <&clk IMX8MN_CLK_A53_CORE>,
0621 <&clk IMX8MN_CLK_NOC>,
0622 <&clk IMX8MN_CLK_AUDIO_AHB>,
0623 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
0624 <&clk IMX8MN_SYS_PLL3>,
0625 <&clk IMX8MN_AUDIO_PLL1>,
0626 <&clk IMX8MN_AUDIO_PLL2>;
0627 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
0628 <&clk IMX8MN_ARM_PLL_OUT>,
0629 <&clk IMX8MN_SYS_PLL3_OUT>,
0630 <&clk IMX8MN_SYS_PLL1_800M>;
0631 assigned-clock-rates = <0>, <0>, <0>,
0632 <400000000>,
0633 <400000000>,
0634 <600000000>,
0635 <393216000>,
0636 <361267200>;
0637 };
0638
0639 src: reset-controller@30390000 {
0640 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
0641 reg = <0x30390000 0x10000>;
0642 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0643 #reset-cells = <1>;
0644 };
0645
0646 gpc: gpc@303a0000 {
0647 compatible = "fsl,imx8mn-gpc";
0648 reg = <0x303a0000 0x10000>;
0649 interrupt-parent = <&gic>;
0650 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0651
0652 pgc {
0653 #address-cells = <1>;
0654 #size-cells = <0>;
0655
0656 pgc_hsiomix: power-domain@0 {
0657 #power-domain-cells = <0>;
0658 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
0659 clocks = <&clk IMX8MN_CLK_USB_BUS>;
0660 };
0661
0662 pgc_otg1: power-domain@1 {
0663 #power-domain-cells = <0>;
0664 reg = <IMX8MN_POWER_DOMAIN_OTG1>;
0665 power-domains = <&pgc_hsiomix>;
0666 };
0667
0668 pgc_gpumix: power-domain@2 {
0669 #power-domain-cells = <0>;
0670 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
0671 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
0672 <&clk IMX8MN_CLK_GPU_SHADER>,
0673 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
0674 <&clk IMX8MN_CLK_GPU_AHB>;
0675 };
0676
0677 pgc_dispmix: power-domain@3 {
0678 #power-domain-cells = <0>;
0679 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
0680 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
0681 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
0682 };
0683
0684 pgc_mipi: power-domain@4 {
0685 #power-domain-cells = <0>;
0686 reg = <IMX8MN_POWER_DOMAIN_MIPI>;
0687 power-domains = <&pgc_dispmix>;
0688 };
0689 };
0690 };
0691 };
0692
0693 aips2: bus@30400000 {
0694 compatible = "fsl,aips-bus", "simple-bus";
0695 reg = <0x30400000 0x400000>;
0696 #address-cells = <1>;
0697 #size-cells = <1>;
0698 ranges;
0699
0700 pwm1: pwm@30660000 {
0701 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
0702 reg = <0x30660000 0x10000>;
0703 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0704 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
0705 <&clk IMX8MN_CLK_PWM1_ROOT>;
0706 clock-names = "ipg", "per";
0707 #pwm-cells = <3>;
0708 status = "disabled";
0709 };
0710
0711 pwm2: pwm@30670000 {
0712 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
0713 reg = <0x30670000 0x10000>;
0714 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0715 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
0716 <&clk IMX8MN_CLK_PWM2_ROOT>;
0717 clock-names = "ipg", "per";
0718 #pwm-cells = <3>;
0719 status = "disabled";
0720 };
0721
0722 pwm3: pwm@30680000 {
0723 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
0724 reg = <0x30680000 0x10000>;
0725 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0726 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
0727 <&clk IMX8MN_CLK_PWM3_ROOT>;
0728 clock-names = "ipg", "per";
0729 #pwm-cells = <3>;
0730 status = "disabled";
0731 };
0732
0733 pwm4: pwm@30690000 {
0734 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
0735 reg = <0x30690000 0x10000>;
0736 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0737 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
0738 <&clk IMX8MN_CLK_PWM4_ROOT>;
0739 clock-names = "ipg", "per";
0740 #pwm-cells = <3>;
0741 status = "disabled";
0742 };
0743
0744 system_counter: timer@306a0000 {
0745 compatible = "nxp,sysctr-timer";
0746 reg = <0x306a0000 0x20000>;
0747 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0748 clocks = <&osc_24m>;
0749 clock-names = "per";
0750 };
0751 };
0752
0753 aips3: bus@30800000 {
0754 compatible = "fsl,aips-bus", "simple-bus";
0755 reg = <0x30800000 0x400000>;
0756 #address-cells = <1>;
0757 #size-cells = <1>;
0758 ranges;
0759
0760 spba1: spba-bus@30800000 {
0761 compatible = "fsl,spba-bus", "simple-bus";
0762 #address-cells = <1>;
0763 #size-cells = <1>;
0764 reg = <0x30800000 0x100000>;
0765 ranges;
0766
0767 ecspi1: spi@30820000 {
0768 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
0769 #address-cells = <1>;
0770 #size-cells = <0>;
0771 reg = <0x30820000 0x10000>;
0772 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0773 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
0774 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
0775 clock-names = "ipg", "per";
0776 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
0777 dma-names = "rx", "tx";
0778 status = "disabled";
0779 };
0780
0781 ecspi2: spi@30830000 {
0782 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
0783 #address-cells = <1>;
0784 #size-cells = <0>;
0785 reg = <0x30830000 0x10000>;
0786 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0787 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
0788 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
0789 clock-names = "ipg", "per";
0790 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
0791 dma-names = "rx", "tx";
0792 status = "disabled";
0793 };
0794
0795 ecspi3: spi@30840000 {
0796 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
0797 #address-cells = <1>;
0798 #size-cells = <0>;
0799 reg = <0x30840000 0x10000>;
0800 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0801 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
0802 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
0803 clock-names = "ipg", "per";
0804 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
0805 dma-names = "rx", "tx";
0806 status = "disabled";
0807 };
0808
0809 uart1: serial@30860000 {
0810 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
0811 reg = <0x30860000 0x10000>;
0812 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0813 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
0814 <&clk IMX8MN_CLK_UART1_ROOT>;
0815 clock-names = "ipg", "per";
0816 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
0817 dma-names = "rx", "tx";
0818 status = "disabled";
0819 };
0820
0821 uart3: serial@30880000 {
0822 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
0823 reg = <0x30880000 0x10000>;
0824 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0825 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
0826 <&clk IMX8MN_CLK_UART3_ROOT>;
0827 clock-names = "ipg", "per";
0828 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
0829 dma-names = "rx", "tx";
0830 status = "disabled";
0831 };
0832
0833 uart2: serial@30890000 {
0834 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
0835 reg = <0x30890000 0x10000>;
0836 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0837 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
0838 <&clk IMX8MN_CLK_UART2_ROOT>;
0839 clock-names = "ipg", "per";
0840 status = "disabled";
0841 };
0842 };
0843
0844 crypto: crypto@30900000 {
0845 compatible = "fsl,sec-v4.0";
0846 #address-cells = <1>;
0847 #size-cells = <1>;
0848 reg = <0x30900000 0x40000>;
0849 ranges = <0 0x30900000 0x40000>;
0850 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0851 clocks = <&clk IMX8MN_CLK_AHB>,
0852 <&clk IMX8MN_CLK_IPG_ROOT>;
0853 clock-names = "aclk", "ipg";
0854
0855 sec_jr0: jr@1000 {
0856 compatible = "fsl,sec-v4.0-job-ring";
0857 reg = <0x1000 0x1000>;
0858 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0859 status = "disabled";
0860 };
0861
0862 sec_jr1: jr@2000 {
0863 compatible = "fsl,sec-v4.0-job-ring";
0864 reg = <0x2000 0x1000>;
0865 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0866 };
0867
0868 sec_jr2: jr@3000 {
0869 compatible = "fsl,sec-v4.0-job-ring";
0870 reg = <0x3000 0x1000>;
0871 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0872 };
0873 };
0874
0875 i2c1: i2c@30a20000 {
0876 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
0877 #address-cells = <1>;
0878 #size-cells = <0>;
0879 reg = <0x30a20000 0x10000>;
0880 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0881 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
0882 status = "disabled";
0883 };
0884
0885 i2c2: i2c@30a30000 {
0886 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
0887 #address-cells = <1>;
0888 #size-cells = <0>;
0889 reg = <0x30a30000 0x10000>;
0890 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0891 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
0892 status = "disabled";
0893 };
0894
0895 i2c3: i2c@30a40000 {
0896 #address-cells = <1>;
0897 #size-cells = <0>;
0898 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
0899 reg = <0x30a40000 0x10000>;
0900 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0901 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
0902 status = "disabled";
0903 };
0904
0905 i2c4: i2c@30a50000 {
0906 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
0907 #address-cells = <1>;
0908 #size-cells = <0>;
0909 reg = <0x30a50000 0x10000>;
0910 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0911 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
0912 status = "disabled";
0913 };
0914
0915 uart4: serial@30a60000 {
0916 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
0917 reg = <0x30a60000 0x10000>;
0918 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0919 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
0920 <&clk IMX8MN_CLK_UART4_ROOT>;
0921 clock-names = "ipg", "per";
0922 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
0923 dma-names = "rx", "tx";
0924 status = "disabled";
0925 };
0926
0927 mu: mailbox@30aa0000 {
0928 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
0929 reg = <0x30aa0000 0x10000>;
0930 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0931 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
0932 #mbox-cells = <2>;
0933 };
0934
0935 usdhc1: mmc@30b40000 {
0936 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
0937 reg = <0x30b40000 0x10000>;
0938 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0939 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
0940 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
0941 <&clk IMX8MN_CLK_USDHC1_ROOT>;
0942 clock-names = "ipg", "ahb", "per";
0943 fsl,tuning-start-tap = <20>;
0944 fsl,tuning-step = <2>;
0945 bus-width = <4>;
0946 status = "disabled";
0947 };
0948
0949 usdhc2: mmc@30b50000 {
0950 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
0951 reg = <0x30b50000 0x10000>;
0952 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0953 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
0954 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
0955 <&clk IMX8MN_CLK_USDHC2_ROOT>;
0956 clock-names = "ipg", "ahb", "per";
0957 fsl,tuning-start-tap = <20>;
0958 fsl,tuning-step = <2>;
0959 bus-width = <4>;
0960 status = "disabled";
0961 };
0962
0963 usdhc3: mmc@30b60000 {
0964 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
0965 reg = <0x30b60000 0x10000>;
0966 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0967 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
0968 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
0969 <&clk IMX8MN_CLK_USDHC3_ROOT>;
0970 clock-names = "ipg", "ahb", "per";
0971 fsl,tuning-start-tap = <20>;
0972 fsl,tuning-step = <2>;
0973 bus-width = <4>;
0974 status = "disabled";
0975 };
0976
0977 flexspi: spi@30bb0000 {
0978 #address-cells = <1>;
0979 #size-cells = <0>;
0980 compatible = "nxp,imx8mm-fspi";
0981 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
0982 reg-names = "fspi_base", "fspi_mmap";
0983 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0984 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
0985 <&clk IMX8MN_CLK_QSPI_ROOT>;
0986 clock-names = "fspi_en", "fspi";
0987 status = "disabled";
0988 };
0989
0990 sdma1: dma-controller@30bd0000 {
0991 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
0992 reg = <0x30bd0000 0x10000>;
0993 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0994 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
0995 <&clk IMX8MN_CLK_AHB>;
0996 clock-names = "ipg", "ahb";
0997 #dma-cells = <3>;
0998 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
0999 };
1000
1001 fec1: ethernet@30be0000 {
1002 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1003 reg = <0x30be0000 0x10000>;
1004 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
1009 <&clk IMX8MN_CLK_ENET1_ROOT>,
1010 <&clk IMX8MN_CLK_ENET_TIMER>,
1011 <&clk IMX8MN_CLK_ENET_REF>,
1012 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1013 clock-names = "ipg", "ahb", "ptp",
1014 "enet_clk_ref", "enet_out";
1015 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1016 <&clk IMX8MN_CLK_ENET_TIMER>,
1017 <&clk IMX8MN_CLK_ENET_REF>,
1018 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1019 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1020 <&clk IMX8MN_SYS_PLL2_100M>,
1021 <&clk IMX8MN_SYS_PLL2_125M>,
1022 <&clk IMX8MN_SYS_PLL2_50M>;
1023 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1024 fsl,num-tx-queues = <3>;
1025 fsl,num-rx-queues = <3>;
1026 nvmem-cells = <&fec_mac_address>;
1027 nvmem-cell-names = "mac-address";
1028 fsl,stop-mode = <&gpr 0x10 3>;
1029 status = "disabled";
1030 };
1031
1032 };
1033
1034 aips4: bus@32c00000 {
1035 compatible = "fsl,aips-bus", "simple-bus";
1036 reg = <0x32c00000 0x400000>;
1037 #address-cells = <1>;
1038 #size-cells = <1>;
1039 ranges;
1040
1041 disp_blk_ctrl: blk-ctrl@32e28000 {
1042 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1043 reg = <0x32e28000 0x100>;
1044 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1045 <&pgc_dispmix>, <&pgc_mipi>,
1046 <&pgc_mipi>;
1047 power-domain-names = "bus", "isi",
1048 "lcdif", "mipi-dsi",
1049 "mipi-csi";
1050 clocks = <&clk IMX8MN_CLK_DISP_AXI>,
1051 <&clk IMX8MN_CLK_DISP_APB>,
1052 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1053 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1054 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1055 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1056 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1057 <&clk IMX8MN_CLK_DSI_CORE>,
1058 <&clk IMX8MN_CLK_DSI_PHY_REF>,
1059 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
1060 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
1061 clock-names = "disp_axi", "disp_apb",
1062 "disp_axi_root", "disp_apb_root",
1063 "lcdif-axi", "lcdif-apb", "lcdif-pix",
1064 "dsi-pclk", "dsi-ref",
1065 "csi-aclk", "csi-pclk";
1066 #power-domain-cells = <1>;
1067 };
1068
1069 usbotg1: usb@32e40000 {
1070 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
1071 reg = <0x32e40000 0x200>;
1072 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
1074 clock-names = "usb1_ctrl_root_clk";
1075 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1076 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
1077 phys = <&usbphynop1>;
1078 fsl,usbmisc = <&usbmisc1 0>;
1079 power-domains = <&pgc_otg1>;
1080 status = "disabled";
1081 };
1082
1083 usbmisc1: usbmisc@32e40200 {
1084 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
1085 #index-cells = <1>;
1086 reg = <0x32e40200 0x200>;
1087 };
1088 };
1089
1090 dma_apbh: dma-controller@33000000 {
1091 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1092 reg = <0x33000000 0x2000>;
1093 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1094 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1097 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1098 #dma-cells = <1>;
1099 dma-channels = <4>;
1100 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1101 };
1102
1103 gpmi: nand-controller@33002000 {
1104 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1105 #address-cells = <1>;
1106 #size-cells = <1>;
1107 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1108 reg-names = "gpmi-nand", "bch";
1109 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupt-names = "bch";
1111 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1112 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1113 clock-names = "gpmi_io", "gpmi_bch_apb";
1114 dmas = <&dma_apbh 0>;
1115 dma-names = "rx-tx";
1116 status = "disabled";
1117 };
1118
1119 gpu: gpu@38000000 {
1120 compatible = "vivante,gc";
1121 reg = <0x38000000 0x8000>;
1122 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1123 clocks = <&clk IMX8MN_CLK_GPU_AHB>,
1124 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
1125 <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
1126 <&clk IMX8MN_CLK_GPU_SHADER>;
1127 clock-names = "reg", "bus", "core", "shader";
1128 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1129 <&clk IMX8MN_CLK_GPU_SHADER>,
1130 <&clk IMX8MN_CLK_GPU_AXI>,
1131 <&clk IMX8MN_CLK_GPU_AHB>,
1132 <&clk IMX8MN_GPU_PLL>;
1133 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1134 <&clk IMX8MN_GPU_PLL_OUT>,
1135 <&clk IMX8MN_SYS_PLL1_800M>,
1136 <&clk IMX8MN_SYS_PLL1_800M>;
1137 assigned-clock-rates = <400000000>,
1138 <400000000>,
1139 <800000000>,
1140 <400000000>,
1141 <1200000000>;
1142 power-domains = <&pgc_gpumix>;
1143 };
1144
1145 gic: interrupt-controller@38800000 {
1146 compatible = "arm,gic-v3";
1147 reg = <0x38800000 0x10000>,
1148 <0x38880000 0xc0000>;
1149 #interrupt-cells = <3>;
1150 interrupt-controller;
1151 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1152 };
1153
1154 ddrc: memory-controller@3d400000 {
1155 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1156 reg = <0x3d400000 0x400000>;
1157 clock-names = "core", "pll", "alt", "apb";
1158 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
1159 <&clk IMX8MN_DRAM_PLL>,
1160 <&clk IMX8MN_CLK_DRAM_ALT>,
1161 <&clk IMX8MN_CLK_DRAM_APB>;
1162 };
1163
1164 ddr-pmu@3d800000 {
1165 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1166 reg = <0x3d800000 0x400000>;
1167 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1168 };
1169 };
1170
1171 usbphynop1: usbphynop1 {
1172 #phy-cells = <0>;
1173 compatible = "usb-nop-xceiv";
1174 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1175 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1176 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1177 clock-names = "main_clk";
1178 };
1179 };
