0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2019-2020 Variscite Ltd.
0004 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "imx8mn-var-som.dtsi"
0010
0011 / {
0012 model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
0013 compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
0014
0015 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
0016 compatible = "regulator-fixed";
0017 pinctrl-names = "default";
0018 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
0019 regulator-name = "VSD_3V3";
0020 regulator-min-microvolt = <3300000>;
0021 regulator-max-microvolt = <3300000>;
0022 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
0023 enable-active-high;
0024 };
0025
0026 gpio-keys {
0027 compatible = "gpio-keys";
0028
0029 key-back {
0030 label = "Back";
0031 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
0032 linux,code = <KEY_BACK>;
0033 };
0034
0035 key-home {
0036 label = "Home";
0037 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
0038 linux,code = <KEY_HOME>;
0039 };
0040
0041 key-menu {
0042 label = "Menu";
0043 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
0044 linux,code = <KEY_MENU>;
0045 };
0046 };
0047
0048 leds {
0049 compatible = "gpio-leds";
0050
0051 led {
0052 label = "Heartbeat";
0053 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
0054 linux,default-trigger = "heartbeat";
0055 };
0056 };
0057 };
0058
0059 ðphy {
0060 reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
0061 };
0062
0063 &i2c2 {
0064 clock-frequency = <400000>;
0065 pinctrl-names = "default";
0066 pinctrl-0 = <&pinctrl_i2c2>;
0067 status = "okay";
0068
0069 pca9534: gpio@20 {
0070 compatible = "nxp,pca9534";
0071 reg = <0x20>;
0072 gpio-controller;
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&pinctrl_pca9534>;
0075 interrupt-parent = <&gpio1>;
0076 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
0077 #gpio-cells = <2>;
0078 wakeup-source;
0079
0080 /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
0081 usb3-sata-sel-hog {
0082 gpio-hog;
0083 gpios = <4 GPIO_ACTIVE_HIGH>;
0084 output-low;
0085 line-name = "usb3_sata_sel";
0086 };
0087
0088 som-vselect-hog {
0089 gpio-hog;
0090 gpios = <6 GPIO_ACTIVE_HIGH>;
0091 output-low;
0092 line-name = "som_vselect";
0093 };
0094
0095 enet-sel-hog {
0096 gpio-hog;
0097 gpios = <7 GPIO_ACTIVE_HIGH>;
0098 output-low;
0099 line-name = "enet_sel";
0100 };
0101 };
0102
0103 extcon_usbotg1: typec@3d {
0104 compatible = "nxp,ptn5150";
0105 reg = <0x3d>;
0106 interrupt-parent = <&gpio1>;
0107 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
0108 pinctrl-names = "default";
0109 pinctrl-0 = <&pinctrl_ptn5150>;
0110 status = "okay";
0111 };
0112 };
0113
0114 &i2c3 {
0115 /* Capacitive touch controller */
0116 ft5x06_ts: touchscreen@38 {
0117 compatible = "edt,edt-ft5406";
0118 reg = <0x38>;
0119 pinctrl-names = "default";
0120 pinctrl-0 = <&pinctrl_captouch>;
0121 interrupt-parent = <&gpio5>;
0122 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
0123
0124 touchscreen-size-x = <800>;
0125 touchscreen-size-y = <480>;
0126 touchscreen-inverted-x;
0127 touchscreen-inverted-y;
0128 };
0129
0130 rtc@68 {
0131 compatible = "dallas,ds1337";
0132 reg = <0x68>;
0133 };
0134 };
0135
0136 /* Header */
0137 &uart1 {
0138 pinctrl-names = "default";
0139 pinctrl-0 = <&pinctrl_uart1>;
0140 status = "okay";
0141 };
0142
0143 /* Header */
0144 &uart3 {
0145 pinctrl-names = "default";
0146 pinctrl-0 = <&pinctrl_uart3>;
0147 status = "okay";
0148 };
0149
0150 &usbotg1 {
0151 disable-over-current;
0152 extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
0153 };
0154
0155 &pinctrl_fec1 {
0156 fsl,pins = <
0157 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0158 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0159 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0160 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0161 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0162 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0163 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0164 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0165 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0166 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0167 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0168 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0169 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0170 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0171 /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
0172 >;
0173 };
0174
0175 &pinctrl_fec1_sleep {
0176 fsl,pins = <
0177 MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
0178 MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
0179 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
0180 MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
0181 MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
0182 MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
0183 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
0184 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
0185 MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
0186 MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
0187 MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
0188 MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
0189 MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
0190 MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
0191 /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
0192 >;
0193 };
0194
0195 &iomuxc {
0196 pinctrl_captouch: captouchgrp {
0197 fsl,pins = <
0198 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
0199 >;
0200 };
0201
0202 pinctrl_i2c2: i2c2grp {
0203 fsl,pins = <
0204 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0205 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0206 >;
0207 };
0208
0209 pinctrl_pca9534: pca9534grp {
0210 fsl,pins = <
0211 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
0212 >;
0213 };
0214
0215 pinctrl_ptn5150: ptn5150grp {
0216 fsl,pins = <
0217 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16
0218 >;
0219 };
0220
0221 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0222 fsl,pins = <
0223 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
0224 >;
0225 };
0226
0227 pinctrl_uart1: uart1grp {
0228 fsl,pins = <
0229 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
0230 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
0231 >;
0232 };
0233
0234 pinctrl_uart3: uart3grp {
0235 fsl,pins = <
0236 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
0237 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
0238 >;
0239 };
0240 };
