0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
0002 /*
0003 * Copyright 2020-2021 TQ-Systems GmbH
0004 */
0005
0006 #include "imx8mn.dtsi"
0007
0008 / {
0009 model = "TQ-Systems i.MX8MN TQMa8MxNL";
0010 compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
0011
0012 memory@40000000 {
0013 device_type = "memory";
0014 /* our minimum RAM config will be 1024 MiB */
0015 reg = <0x00000000 0x40000000 0 0x40000000>;
0016 };
0017
0018 /* e-MMC IO, needed for HS modes */
0019 reg_vcc1v8: regulator-vcc1v8 {
0020 compatible = "regulator-fixed";
0021 regulator-name = "TQMA8MXNL_VCC1V8";
0022 regulator-min-microvolt = <1800000>;
0023 regulator-max-microvolt = <1800000>;
0024 };
0025
0026 reg_vcc3v3: regulator-vcc3v3 {
0027 compatible = "regulator-fixed";
0028 regulator-name = "TQMA8MXNL_VCC3V3";
0029 regulator-min-microvolt = <3300000>;
0030 regulator-max-microvolt = <3300000>;
0031 };
0032
0033 reserved-memory {
0034 #address-cells = <2>;
0035 #size-cells = <2>;
0036 ranges;
0037
0038 /* global autoconfigured region for contiguous allocations */
0039 linux,cma {
0040 compatible = "shared-dma-pool";
0041 reusable;
0042 /* 640 MiB */
0043 size = <0 0x28000000>;
0044 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
0045 alloc-ranges = <0 0x40000000 0 0x78000000>;
0046 linux,cma-default;
0047 };
0048 };
0049 };
0050
0051 &A53_0 {
0052 cpu-supply = <&buck2_reg>;
0053 };
0054
0055 &flexspi {
0056 pinctrl-names = "default";
0057 pinctrl-0 = <&pinctrl_flexspi>;
0058 status = "okay";
0059
0060 flash0: flash@0 {
0061 compatible = "jedec,spi-nor";
0062 reg = <0>;
0063 #address-cells = <1>;
0064 #size-cells = <1>;
0065 spi-max-frequency = <84000000>;
0066 spi-tx-bus-width = <1>;
0067 spi-rx-bus-width = <4>;
0068 };
0069 };
0070
0071 &i2c1 {
0072 clock-frequency = <100000>;
0073 pinctrl-names = "default", "gpio";
0074 pinctrl-0 = <&pinctrl_i2c1>;
0075 pinctrl-1 = <&pinctrl_i2c1_gpio>;
0076 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0077 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
0078 status = "okay";
0079
0080 sensor0: temperature-sensor-eeprom@1b {
0081 compatible = "nxp,se97", "jedec,jc-42.4-temp";
0082 reg = <0x1b>;
0083 };
0084
0085 pca9450: pmic@25 {
0086 compatible = "nxp,pca9450a";
0087 reg = <0x25>;
0088
0089 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
0090 pinctrl-0 = <&pinctrl_pmic>;
0091 pinctrl-names = "default";
0092 interrupt-parent = <&gpio1>;
0093 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0094
0095 regulators {
0096 /* V_0V85_SOC: 0.85 .. 0.95 */
0097 buck1_reg: BUCK1 {
0098 regulator-name = "BUCK1";
0099 regulator-min-microvolt = <850000>;
0100 regulator-max-microvolt = <950000>;
0101 regulator-boot-on;
0102 regulator-always-on;
0103 regulator-ramp-delay = <3125>;
0104 };
0105
0106 /* VDD_ARM */
0107 buck2_reg: BUCK2 {
0108 regulator-name = "BUCK2";
0109 regulator-min-microvolt = <850000>;
0110 regulator-max-microvolt = <1000000>;
0111 regulator-boot-on;
0112 regulator-always-on;
0113 nxp,dvs-run-voltage = <950000>;
0114 nxp,dvs-standby-voltage = <850000>;
0115 regulator-ramp-delay = <3125>;
0116 };
0117
0118 /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */
0119 buck3_reg: BUCK3 {
0120 regulator-name = "BUCK3";
0121 regulator-min-microvolt = <850000>;
0122 regulator-max-microvolt = <950000>;
0123 regulator-boot-on;
0124 regulator-always-on;
0125 regulator-ramp-delay = <3125>;
0126 };
0127
0128 /* VCC3V3 -> VMMC, ... must not be changed */
0129 buck4_reg: BUCK4 {
0130 regulator-name = "BUCK4";
0131 regulator-min-microvolt = <3300000>;
0132 regulator-max-microvolt = <3300000>;
0133 regulator-boot-on;
0134 regulator-always-on;
0135 };
0136
0137 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
0138 buck5_reg: BUCK5 {
0139 regulator-name = "BUCK5";
0140 regulator-min-microvolt = <1800000>;
0141 regulator-max-microvolt = <1800000>;
0142 regulator-boot-on;
0143 regulator-always-on;
0144 };
0145
0146 /* V_1V1 -> RAM, ... must not be changed */
0147 buck6_reg: BUCK6 {
0148 regulator-name = "BUCK6";
0149 regulator-min-microvolt = <1100000>;
0150 regulator-max-microvolt = <1100000>;
0151 regulator-boot-on;
0152 regulator-always-on;
0153 };
0154
0155 /* V_1V8_SNVS */
0156 ldo1_reg: LDO1 {
0157 regulator-name = "LDO1";
0158 regulator-min-microvolt = <1800000>;
0159 regulator-max-microvolt = <1800000>;
0160 regulator-boot-on;
0161 regulator-always-on;
0162 };
0163
0164 /* V_0V8_SNVS */
0165 ldo2_reg: LDO2 {
0166 regulator-name = "LDO2";
0167 regulator-min-microvolt = <800000>;
0168 regulator-max-microvolt = <850000>;
0169 regulator-boot-on;
0170 regulator-always-on;
0171 };
0172
0173 /* V_1V8_ANA */
0174 ldo3_reg: LDO3 {
0175 regulator-name = "LDO3";
0176 regulator-min-microvolt = <1800000>;
0177 regulator-max-microvolt = <1800000>;
0178 regulator-boot-on;
0179 regulator-always-on;
0180 };
0181
0182 /* V_0V9_MIPI */
0183 ldo4_reg: LDO4 {
0184 regulator-name = "LDO4";
0185 regulator-min-microvolt = <900000>;
0186 regulator-max-microvolt = <900000>;
0187 regulator-boot-on;
0188 regulator-always-on;
0189 };
0190
0191 /* VCC SD IO - switched using SD2 VSELECT */
0192 ldo5_reg: LDO5 {
0193 regulator-name = "LDO5";
0194 regulator-min-microvolt = <1800000>;
0195 regulator-max-microvolt = <3300000>;
0196 };
0197 };
0198 };
0199
0200 pcf85063: rtc@51 {
0201 compatible = "nxp,pcf85063a";
0202 reg = <0x51>;
0203 quartz-load-femtofarads = <7000>;
0204 };
0205
0206 eeprom1: eeprom@53 {
0207 compatible = "nxp,se97b", "atmel,24c02";
0208 read-only;
0209 reg = <0x53>;
0210 pagesize = <16>;
0211 };
0212
0213 eeprom0: eeprom@57 {
0214 compatible = "atmel,24c64";
0215 reg = <0x57>;
0216 pagesize = <32>;
0217 };
0218 };
0219
0220 &usdhc3 {
0221 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0222 pinctrl-0 = <&pinctrl_usdhc3>;
0223 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0224 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0225 bus-width = <8>;
0226 non-removable;
0227 no-sd;
0228 no-sdio;
0229 vmmc-supply = <®_vcc3v3>;
0230 vqmmc-supply = <®_vcc1v8>;
0231 status = "okay";
0232 };
0233
0234 /*
0235 * Attention:
0236 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
0237 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
0238 */
0239 &wdog1 {
0240 pinctrl-names = "default";
0241 pinctrl-0 = <&pinctrl_wdog>;
0242 fsl,ext-reset-output;
0243 status = "okay";
0244 };
0245
0246 &iomuxc {
0247 pinctrl_flexspi: flexspigrp {
0248 fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x84>,
0249 <MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84>,
0250 <MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84>,
0251 <MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84>,
0252 <MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84>,
0253 <MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84>;
0254 };
0255
0256 pinctrl_i2c1: i2c1grp {
0257 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c4>,
0258 <MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c4>;
0259 };
0260
0261 pinctrl_i2c1_gpio: i2c1gpiogrp {
0262 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c4>,
0263 <MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c4>;
0264 };
0265
0266 pinctrl_pmic: pmicgrp {
0267 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>;
0268 };
0269
0270 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0271 fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
0272 };
0273
0274 pinctrl_usdhc3: usdhc3grp {
0275 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
0276 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
0277 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
0278 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
0279 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
0280 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
0281 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
0282 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
0283 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
0284 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
0285 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
0286 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
0287 };
0288
0289 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0290 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
0291 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
0292 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
0293 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
0294 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
0295 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
0296 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
0297 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
0298 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
0299 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
0300 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
0301 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
0302 };
0303
0304 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0305 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
0306 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
0307 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
0308 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
0309 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
0310 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
0311 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
0312 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
0313 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
0314 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
0315 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
0316 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
0317 };
0318
0319 pinctrl_wdog: wdoggrp {
0320 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;
0321 };
0322 };
