0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright 2019 NXP
0004 */
0005
0006 #include <dt-bindings/usb/pd.h>
0007 #include "imx8mn.dtsi"
0008
0009 / {
0010 chosen {
0011 stdout-path = &uart2;
0012 };
0013
0014 gpio-leds {
0015 compatible = "gpio-leds";
0016 pinctrl-names = "default";
0017 pinctrl-0 = <&pinctrl_gpio_led>;
0018
0019 status {
0020 label = "yellow:status";
0021 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
0022 default-state = "on";
0023 };
0024 };
0025
0026 memory@40000000 {
0027 device_type = "memory";
0028 reg = <0x0 0x40000000 0 0x80000000>;
0029 };
0030
0031 reg_usdhc2_vmmc: regulator-usdhc2 {
0032 compatible = "regulator-fixed";
0033 pinctrl-names = "default";
0034 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
0035 regulator-name = "VSD_3V3";
0036 regulator-min-microvolt = <3300000>;
0037 regulator-max-microvolt = <3300000>;
0038 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
0039 enable-active-high;
0040 };
0041
0042 ir-receiver {
0043 compatible = "gpio-ir-receiver";
0044 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
0045 pinctrl-names = "default";
0046 pinctrl-0 = <&pinctrl_ir>;
0047 linux,autosuspend-period = <125>;
0048 };
0049
0050 audio_codec_bt_sco: audio-codec-bt-sco {
0051 compatible = "linux,bt-sco";
0052 #sound-dai-cells = <1>;
0053 };
0054
0055 wm8524: audio-codec {
0056 #sound-dai-cells = <0>;
0057 compatible = "wlf,wm8524";
0058 pinctrl-names = "default";
0059 pinctrl-0 = <&pinctrl_gpio_wlf>;
0060 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
0061 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
0062 clock-names = "mclk";
0063 };
0064
0065 sound-bt-sco {
0066 compatible = "simple-audio-card";
0067 simple-audio-card,name = "bt-sco-audio";
0068 simple-audio-card,format = "dsp_a";
0069 simple-audio-card,bitclock-inversion;
0070 simple-audio-card,frame-master = <&btcpu>;
0071 simple-audio-card,bitclock-master = <&btcpu>;
0072
0073 btcpu: simple-audio-card,cpu {
0074 sound-dai = <&sai2>;
0075 dai-tdm-slot-num = <2>;
0076 dai-tdm-slot-width = <16>;
0077 };
0078
0079 simple-audio-card,codec {
0080 sound-dai = <&audio_codec_bt_sco 1>;
0081 };
0082 };
0083
0084 sound-wm8524 {
0085 compatible = "fsl,imx-audio-wm8524";
0086 model = "wm8524-audio";
0087 audio-cpu = <&sai3>;
0088 audio-codec = <&wm8524>;
0089 audio-asrc = <&easrc>;
0090 audio-routing =
0091 "Line Out Jack", "LINEVOUTL",
0092 "Line Out Jack", "LINEVOUTR";
0093 };
0094
0095 sound-spdif {
0096 compatible = "fsl,imx-audio-spdif";
0097 model = "imx-spdif";
0098 spdif-controller = <&spdif1>;
0099 spdif-out;
0100 spdif-in;
0101 };
0102 };
0103
0104 &easrc {
0105 fsl,asrc-rate = <48000>;
0106 status = "okay";
0107 };
0108
0109 &fec1 {
0110 pinctrl-names = "default";
0111 pinctrl-0 = <&pinctrl_fec1>;
0112 phy-mode = "rgmii-id";
0113 phy-handle = <ðphy0>;
0114 fsl,magic-packet;
0115 status = "okay";
0116
0117 mdio {
0118 #address-cells = <1>;
0119 #size-cells = <0>;
0120
0121 ethphy0: ethernet-phy@0 {
0122 compatible = "ethernet-phy-ieee802.3-c22";
0123 reg = <0>;
0124 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
0125 reset-assert-us = <10000>;
0126 qca,disable-smarteee;
0127 vddio-supply = <&vddio>;
0128
0129 vddio: vddio-regulator {
0130 regulator-min-microvolt = <1800000>;
0131 regulator-max-microvolt = <1800000>;
0132 };
0133 };
0134 };
0135 };
0136
0137 &flexspi {
0138 pinctrl-names = "default";
0139 pinctrl-0 = <&pinctrl_flexspi>;
0140 status = "okay";
0141
0142 flash0: flash@0 {
0143 compatible = "jedec,spi-nor";
0144 reg = <0>;
0145 #address-cells = <1>;
0146 #size-cells = <1>;
0147 spi-max-frequency = <166000000>;
0148 spi-tx-bus-width = <4>;
0149 spi-rx-bus-width = <4>;
0150 };
0151 };
0152
0153 &i2c1 {
0154 clock-frequency = <400000>;
0155 pinctrl-names = "default";
0156 pinctrl-0 = <&pinctrl_i2c1>;
0157 status = "okay";
0158 };
0159
0160 &i2c2 {
0161 clock-frequency = <400000>;
0162 pinctrl-names = "default";
0163 pinctrl-0 = <&pinctrl_i2c2>;
0164 status = "okay";
0165
0166 ptn5110: tcpc@50 {
0167 compatible = "nxp,ptn5110";
0168 pinctrl-names = "default";
0169 pinctrl-0 = <&pinctrl_typec1>;
0170 reg = <0x50>;
0171 interrupt-parent = <&gpio2>;
0172 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
0173 status = "okay";
0174
0175 port {
0176 typec1_dr_sw: endpoint {
0177 remote-endpoint = <&usb1_drd_sw>;
0178 };
0179 };
0180
0181 typec1_con: connector {
0182 compatible = "usb-c-connector";
0183 label = "USB-C";
0184 power-role = "dual";
0185 data-role = "dual";
0186 try-power-role = "sink";
0187 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
0188 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
0189 PDO_VAR(5000, 20000, 3000)>;
0190 op-sink-microwatt = <15000000>;
0191 self-powered;
0192 };
0193 };
0194 };
0195
0196 &i2c3 {
0197 clock-frequency = <400000>;
0198 pinctrl-names = "default";
0199 pinctrl-0 = <&pinctrl_i2c3>;
0200 status = "okay";
0201
0202 pca6416: gpio@20 {
0203 compatible = "ti,tca6416";
0204 reg = <0x20>;
0205 gpio-controller;
0206 #gpio-cells = <2>;
0207 };
0208 };
0209
0210 &sai2 {
0211 #sound-dai-cells = <0>;
0212 pinctrl-names = "default";
0213 pinctrl-0 = <&pinctrl_sai2>;
0214 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
0215 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
0216 assigned-clock-rates = <24576000>;
0217 status = "okay";
0218 };
0219
0220 &sai3 {
0221 pinctrl-names = "default";
0222 pinctrl-0 = <&pinctrl_sai3>;
0223 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
0224 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
0225 assigned-clock-rates = <24576000>;
0226 fsl,sai-mclk-direction-output;
0227 status = "okay";
0228 };
0229
0230 &snvs_pwrkey {
0231 status = "okay";
0232 };
0233
0234 &spdif1 {
0235 pinctrl-names = "default";
0236 pinctrl-0 = <&pinctrl_spdif1>;
0237 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
0238 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
0239 assigned-clock-rates = <24576000>;
0240 status = "okay";
0241 };
0242
0243 &uart2 { /* console */
0244 pinctrl-names = "default";
0245 pinctrl-0 = <&pinctrl_uart2>;
0246 status = "okay";
0247 };
0248
0249 &uart3 {
0250 pinctrl-names = "default";
0251 pinctrl-0 = <&pinctrl_uart3>;
0252 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
0253 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
0254 uart-has-rtscts;
0255 status = "okay";
0256 };
0257
0258 &usbotg1 {
0259 dr_mode = "otg";
0260 hnp-disable;
0261 srp-disable;
0262 adp-disable;
0263 usb-role-switch;
0264 disable-over-current;
0265 samsung,picophy-pre-emp-curr-control = <3>;
0266 samsung,picophy-dc-vol-level-adjust = <7>;
0267 status = "okay";
0268
0269 port {
0270 usb1_drd_sw: endpoint {
0271 remote-endpoint = <&typec1_dr_sw>;
0272 };
0273 };
0274 };
0275
0276 &usdhc2 {
0277 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
0278 assigned-clock-rates = <200000000>;
0279 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0280 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
0281 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
0282 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
0283 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
0284 bus-width = <4>;
0285 vmmc-supply = <®_usdhc2_vmmc>;
0286 status = "okay";
0287 };
0288
0289 &usdhc3 {
0290 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
0291 assigned-clock-rates = <400000000>;
0292 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0293 pinctrl-0 = <&pinctrl_usdhc3>;
0294 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
0295 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
0296 bus-width = <8>;
0297 non-removable;
0298 status = "okay";
0299 };
0300
0301 &wdog1 {
0302 pinctrl-names = "default";
0303 pinctrl-0 = <&pinctrl_wdog>;
0304 fsl,ext-reset-output;
0305 status = "okay";
0306 };
0307
0308 &iomuxc {
0309 pinctrl_fec1: fec1grp {
0310 fsl,pins = <
0311 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
0312 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
0313 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
0314 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
0315 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
0316 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
0317 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
0318 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
0319 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
0320 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
0321 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
0322 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
0323 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
0324 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
0325 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
0326 >;
0327 };
0328
0329 pinctrl_flexspi: flexspigrp {
0330 fsl,pins = <
0331 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
0332 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
0333 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
0334 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
0335 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
0336 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
0337 >;
0338 };
0339
0340 pinctrl_gpio_led: gpioledgrp {
0341 fsl,pins = <
0342 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
0343 >;
0344 };
0345
0346 pinctrl_gpio_wlf: gpiowlfgrp {
0347 fsl,pins = <
0348 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
0349 >;
0350 };
0351
0352 pinctrl_ir: irgrp {
0353 fsl,pins = <
0354 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
0355 >;
0356 };
0357
0358 pinctrl_i2c1: i2c1grp {
0359 fsl,pins = <
0360 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
0361 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
0362 >;
0363 };
0364
0365 pinctrl_i2c2: i2c2grp {
0366 fsl,pins = <
0367 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
0368 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
0369 >;
0370 };
0371
0372 pinctrl_i2c3: i2c3grp {
0373 fsl,pins = <
0374 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
0375 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
0376 >;
0377 };
0378
0379 pinctrl_pmic: pmicirqgrp {
0380 fsl,pins = <
0381 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
0382 >;
0383 };
0384
0385 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
0386 fsl,pins = <
0387 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
0388 >;
0389 };
0390
0391 pinctrl_sai2: sai2grp {
0392 fsl,pins = <
0393 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
0394 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
0395 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
0396 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
0397 >;
0398 };
0399
0400 pinctrl_sai3: sai3grp {
0401 fsl,pins = <
0402 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
0403 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
0404 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
0405 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
0406 >;
0407 };
0408
0409 pinctrl_spdif1: spdif1grp {
0410 fsl,pins = <
0411 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
0412 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
0413 >;
0414 };
0415
0416 pinctrl_typec1: typec1grp {
0417 fsl,pins = <
0418 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
0419 >;
0420 };
0421
0422 pinctrl_uart2: uart2grp {
0423 fsl,pins = <
0424 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
0425 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
0426 >;
0427 };
0428
0429 pinctrl_uart3: uart3grp {
0430 fsl,pins = <
0431 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
0432 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
0433 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
0434 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
0435 >;
0436 };
0437
0438 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
0439 fsl,pins = <
0440 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
0441 >;
0442 };
0443
0444 pinctrl_usdhc2: usdhc2grp {
0445 fsl,pins = <
0446 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
0447 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
0448 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
0449 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
0450 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
0451 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
0452 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0453 >;
0454 };
0455
0456 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
0457 fsl,pins = <
0458 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
0459 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
0460 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
0461 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
0462 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
0463 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
0464 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0465 >;
0466 };
0467
0468 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
0469 fsl,pins = <
0470 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
0471 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
0472 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
0473 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
0474 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
0475 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
0476 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
0477 >;
0478 };
0479
0480 pinctrl_usdhc3: usdhc3grp {
0481 fsl,pins = <
0482 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
0483 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
0484 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
0485 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
0486 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
0487 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
0488 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
0489 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
0490 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
0491 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
0492 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
0493 >;
0494 };
0495
0496 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
0497 fsl,pins = <
0498 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
0499 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
0500 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
0501 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
0502 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
0503 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
0504 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
0505 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
0506 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
0507 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
0508 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
0509 >;
0510 };
0511
0512 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
0513 fsl,pins = <
0514 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
0515 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
0516 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
0517 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
0518 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
0519 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
0520 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
0521 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
0522 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
0523 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
0524 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
0525 >;
0526 };
0527
0528 pinctrl_wdog: wdoggrp {
0529 fsl,pins = <
0530 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
0531 >;
0532 };
0533 };
