0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2021 Collabora Ltd.
0004 * Copyright 2021 BSH Hausgeraete GmbH
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "imx8mn-bsh-smm-s2-common.dtsi"
0010 #include <dt-bindings/sound/tlv320aic31xx.h>
0011
0012 / {
0013 model = "BSH SMM S2 PRO";
0014 compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";
0015
0016 memory@40000000 {
0017 device_type = "memory";
0018 reg = <0x0 0x40000000 0x0 0x20000000>;
0019 };
0020
0021 sound-tlv320aic31xx {
0022 compatible = "fsl,imx-audio-tlv320aic31xx";
0023 model = "tlv320aic31xx-hifi";
0024 audio-cpu = <&sai3>;
0025 audio-codec = <&tlv320dac3101>;
0026 audio-asrc = <&easrc>;
0027 audio-routing =
0028 "Ext Spk", "SPL",
0029 "Ext Spk", "SPR";
0030 mclk-id = <PLL_CLKIN_BCLK>;
0031 };
0032
0033 vdd_input: vdd_input {
0034 compatible = "regulator-fixed";
0035 regulator-name = "vdd_input";
0036 regulator-min-microvolt = <5000000>;
0037 regulator-max-microvolt = <5000000>;
0038 };
0039 };
0040
0041 &easrc {
0042 fsl,asrc-rate = <48000>;
0043 fsl,asrc-format = <10>;
0044 status = "okay";
0045 };
0046
0047 &i2c2 {
0048 clock-frequency = <400000>;
0049 pinctrl-names = "default";
0050 pinctrl-0 = <&pinctrl_i2c2>;
0051 status = "okay";
0052
0053 tlv320dac3101: audio-codec@18 {
0054 compatible = "ti,tlv320dac3101";
0055 pinctrl-names = "default";
0056 pinctrl-0 = <&pinctrl_dac_rst>;
0057 reg = <0x18>;
0058 #sound-dai-cells = <0>;
0059 HPVDD-supply = <&buck4_reg>;
0060 SPRVDD-supply = <&vdd_input>;
0061 SPLVDD-supply = <&vdd_input>;
0062 AVDD-supply = <&buck4_reg>;
0063 IOVDD-supply = <&buck4_reg>;
0064 DVDD-supply = <&buck5_reg>;
0065 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
0066 ai31xx-micbias-vg = <MICBIAS_AVDDV>;
0067 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
0068 };
0069 };
0070
0071 &sai3 {
0072 pinctrl-names = "default";
0073 pinctrl-0 = <&pinctrl_sai3>;
0074 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
0075 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
0076 assigned-clock-rates = <24576000>;
0077 fsl,sai-mclk-direction-output;
0078 status = "okay";
0079 };
0080
0081 /* eMMC */
0082 &usdhc1 {
0083 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0084 pinctrl-0 = <&pinctrl_usdhc1>;
0085 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
0086 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
0087 bus-width = <8>;
0088 non-removable;
0089 status = "okay";
0090 };
0091
0092 &iomuxc {
0093 pinctrl_dac_rst: dacrstgrp {
0094 fsl,pins = <
0095 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */
0096 >;
0097 };
0098
0099 pinctrl_espi2: espi2grp {
0100 fsl,pins = <
0101 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
0102 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
0103 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
0104 MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
0105 >;
0106 };
0107
0108 pinctrl_i2c2: i2c2grp {
0109 fsl,pins = <
0110 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3
0111 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3
0112 >;
0113 };
0114
0115 pinctrl_sai3: sai3grp {
0116 fsl,pins = <
0117 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
0118 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
0119 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
0120 >;
0121 };
0122
0123 pinctrl_usdhc1: usdhc1grp {
0124 fsl,pins = <
0125 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090
0126 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0
0127 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0
0128 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0
0129 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0
0130 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0
0131 MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0
0132 MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0
0133 MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0
0134 MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0
0135 MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090
0136 >;
0137 };
0138
0139 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
0140 fsl,pins = <
0141 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
0142 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
0143 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4
0144 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4
0145 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4
0146 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4
0147 MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4
0148 MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4
0149 MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4
0150 MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4
0151 MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094
0152 >;
0153 };
0154
0155 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
0156 fsl,pins = <
0157 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
0158 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6
0159 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6
0160 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6
0161 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6
0162 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6
0163 MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6
0164 MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6
0165 MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6
0166 MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6
0167 MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096
0168 >;
0169 };
0170 };
