0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright 2021 Collabora Ltd.
0004 * Copyright 2021 BSH Hausgeraete GmbH
0005 */
0006
0007 /dts-v1/;
0008
0009 #include "imx8mn.dtsi"
0010
0011 / {
0012 chosen {
0013 stdout-path = &uart4;
0014 };
0015
0016 fec_supply: fec-supply-en {
0017 compatible = "regulator-fixed";
0018 vin-supply = <&buck4_reg>;
0019 regulator-name = "tja1101_en";
0020 regulator-min-microvolt = <3300000>;
0021 regulator-max-microvolt = <3300000>;
0022 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
0023 enable-active-high;
0024 };
0025
0026 usdhc2_pwrseq: usdhc2-pwrseq {
0027 compatible = "mmc-pwrseq-simple";
0028 pinctrl-names = "default";
0029 pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
0030 reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
0031 };
0032 };
0033
0034 &A53_0 {
0035 cpu-supply = <&buck2_reg>;
0036 };
0037
0038 &A53_1 {
0039 cpu-supply = <&buck2_reg>;
0040 };
0041
0042 &A53_2 {
0043 cpu-supply = <&buck2_reg>;
0044 };
0045
0046 &A53_3 {
0047 cpu-supply = <&buck2_reg>;
0048 };
0049
0050 &ecspi2 {
0051 pinctrl-names = "default";
0052 pinctrl-0 = <&pinctrl_espi2>;
0053 status = "okay";
0054 };
0055
0056 &fec1 {
0057 pinctrl-names = "default";
0058 pinctrl-0 = <&pinctrl_fec1>;
0059 phy-mode = "rmii";
0060 phy-handle = <ðphy0>;
0061 phy-supply = <&fec_supply>;
0062 fsl,magic-packet;
0063 status = "okay";
0064
0065 mdio {
0066 #address-cells = <1>;
0067 #size-cells = <0>;
0068
0069 ethphy0: ethernet-phy@0 {
0070 compatible = "ethernet-phy-ieee802.3-c22";
0071 reg = <0>;
0072 reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
0073 reset-assert-us = <20>;
0074 reset-deassert-us = <2000>;
0075 };
0076 };
0077 };
0078
0079 &i2c1 {
0080 clock-frequency = <400000>;
0081 pinctrl-names = "default";
0082 pinctrl-0 = <&pinctrl_i2c1>;
0083 status = "okay";
0084
0085 bd71847: pmic@4b {
0086 compatible = "rohm,bd71847";
0087 reg = <0x4b>;
0088 pinctrl-names = "default";
0089 pinctrl-0 = <&pinctrl_pmic>;
0090 interrupt-parent = <&gpio1>;
0091 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
0092 rohm,reset-snvs-powered;
0093
0094 #clock-cells = <0>;
0095 clocks = <&osc_32k 0>;
0096 clock-output-names = "clk-32k-out";
0097
0098 regulators {
0099 buck1_reg: BUCK1 {
0100 /* PMIC_BUCK1 - VDD_SOC */
0101 regulator-name = "buck1";
0102 regulator-min-microvolt = <700000>;
0103 regulator-max-microvolt = <1300000>;
0104 regulator-boot-on;
0105 regulator-always-on;
0106 regulator-ramp-delay = <1250>;
0107 };
0108
0109 buck2_reg: BUCK2 {
0110 /* PMIC_BUCK2 - VDD_ARM */
0111 regulator-name = "buck2";
0112 regulator-min-microvolt = <700000>;
0113 regulator-max-microvolt = <1300000>;
0114 regulator-boot-on;
0115 regulator-always-on;
0116 regulator-ramp-delay = <1250>;
0117 };
0118
0119 buck3_reg: BUCK3 {
0120 /* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */
0121 regulator-name = "buck3";
0122 regulator-min-microvolt = <700000>;
0123 regulator-max-microvolt = <1350000>;
0124 regulator-boot-on;
0125 regulator-always-on;
0126 };
0127
0128 buck4_reg: BUCK4 {
0129 /* PMIC_BUCK6 - VDD_3V3 */
0130 regulator-name = "buck4";
0131 regulator-min-microvolt = <3000000>;
0132 regulator-max-microvolt = <3300000>;
0133 regulator-boot-on;
0134 regulator-always-on;
0135 };
0136
0137 buck5_reg: BUCK5 {
0138 /* PMIC_BUCK7 - VDD_1V8 */
0139 regulator-name = "buck5";
0140 regulator-min-microvolt = <1605000>;
0141 regulator-max-microvolt = <1995000>;
0142 regulator-boot-on;
0143 regulator-always-on;
0144 };
0145
0146 buck6_reg: BUCK6 {
0147 /* PMIC_BUCK8 - NVCC_DRAM */
0148 regulator-name = "buck6";
0149 regulator-min-microvolt = <800000>;
0150 regulator-max-microvolt = <1400000>;
0151 regulator-boot-on;
0152 regulator-always-on;
0153 };
0154
0155 ldo1_reg: LDO1 {
0156 /* PMIC_LDO1 - NVCC_SNVS_1V8 */
0157 regulator-name = "ldo1";
0158 regulator-min-microvolt = <1600000>;
0159 regulator-max-microvolt = <1900000>;
0160 regulator-boot-on;
0161 regulator-always-on;
0162 };
0163
0164 ldo2_reg: LDO2 {
0165 /* PMIC_LDO2 - VDD_SNVS_0V8 */
0166 regulator-name = "ldo2";
0167 regulator-min-microvolt = <800000>;
0168 regulator-max-microvolt = <900000>;
0169 regulator-boot-on;
0170 regulator-always-on;
0171 };
0172
0173 ldo3_reg: LDO3 {
0174 /* PMIC_LDO3 - VDDA_1V8 */
0175 regulator-name = "ldo3";
0176 regulator-min-microvolt = <1800000>;
0177 regulator-max-microvolt = <3300000>;
0178 regulator-boot-on;
0179 regulator-always-on;
0180 };
0181
0182 ldo4_reg: LDO4 {
0183 /* PMIC_LDO4 - VDD_MIPI_0V9 */
0184 regulator-name = "ldo4";
0185 regulator-min-microvolt = <900000>;
0186 regulator-max-microvolt = <1800000>;
0187 regulator-boot-on;
0188 regulator-always-on;
0189 };
0190
0191 ldo6_reg: LDO6 {
0192 /* PMIC_LDO6 - VDD_MIPI_1V2 */
0193 regulator-name = "ldo6";
0194 regulator-min-microvolt = <900000>;
0195 regulator-max-microvolt = <1800000>;
0196 regulator-boot-on;
0197 regulator-always-on;
0198 };
0199 };
0200 };
0201 };
0202
0203 &i2c3 {
0204 clock-frequency = <400000>;
0205 pinctrl-names = "default";
0206 pinctrl-0 = <&pinctrl_i2c3>;
0207 status = "okay";
0208 };
0209
0210 &i2c4 {
0211 clock-frequency = <400000>;
0212 pinctrl-names = "default";
0213 pinctrl-0 = <&pinctrl_i2c4>;
0214 status = "okay";
0215 };
0216
0217 &uart2 {
0218 pinctrl-names = "default";
0219 pinctrl-0 = <&pinctrl_uart2>;
0220 status = "okay";
0221 };
0222
0223 &uart3 {
0224 pinctrl-names = "default";
0225 pinctrl-0 = <&pinctrl_uart3>;
0226 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
0227 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
0228 uart-has-rtscts;
0229 status = "okay";
0230
0231 bluetooth {
0232 compatible = "brcm,bcm43438-bt";
0233 pinctrl-names = "default";
0234 pinctrl-0 = <&pinctrl_bluetooth>;
0235 shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
0236 device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
0237 host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
0238 max-speed = <3000000>;
0239 };
0240 };
0241
0242 /* Console */
0243 &uart4 {
0244 pinctrl-names = "default";
0245 pinctrl-0 = <&pinctrl_uart4>;
0246 status = "okay";
0247 };
0248
0249 &usbotg1 {
0250 dr_mode = "peripheral";
0251 disable-over-current;
0252 status = "okay";
0253 };
0254
0255 &usdhc2 {
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258 pinctrl-names = "default", "state_100mhz", "state_200mhz";
0259 pinctrl-0 = <&pinctrl_usdhc2>;
0260 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
0261 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
0262 mmc-pwrseq = <&usdhc2_pwrseq>;
0263 bus-width = <4>;
0264 non-removable;
0265 status = "okay";
0266
0267 brcmf: bcrmf@1 {
0268 compatible = "brcm,bcm4329-fmac";
0269 reg = <1>;
0270 pinctrl-names = "default";
0271 pinctrl-0 = <&pinctrl_wlan>;
0272 interrupt-parent = <&gpio1>;
0273 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
0274 interrupt-names = "host-wake";
0275 };
0276 };
0277
0278 &wdog1 {
0279 pinctrl-names = "default";
0280 pinctrl-0 = <&pinctrl_wdog>;
0281 fsl,ext-reset-output;
0282 status = "okay";
0283 };
0284
0285 &iomuxc {
0286 pinctrl_bluetooth: bluetoothgrp {
0287 fsl,pins = <
0288 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
0289 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
0290 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
0291 >;
0292 };
0293
0294 pinctrl_espi2: espi2grp {
0295 fsl,pins = <
0296 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
0297 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
0298 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
0299 MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
0300 >;
0301 };
0302
0303 pinctrl_fec1: fec1grp {
0304 fsl,pins = <
0305 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
0306 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
0307 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
0308 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
0309 MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
0310 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
0311 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
0312 MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
0313 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
0314 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
0315 MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
0316 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
0317 MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
0318 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
0319 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
0320 >;
0321 };
0322
0323 pinctrl_i2c1: i2c1grp {
0324 fsl,pins = <
0325 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2
0326 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2
0327 >;
0328 };
0329
0330 pinctrl_i2c3: i2c3grp {
0331 fsl,pins = <
0332 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2
0333 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2
0334 >;
0335 };
0336
0337 pinctrl_i2c4: i2c4grp {
0338 fsl,pins = <
0339 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2
0340 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2
0341 >;
0342 };
0343
0344 pinctrl_pmic: pmicirq {
0345 fsl,pins = <
0346 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
0347 >;
0348 };
0349
0350 pinctrl_uart2: uart2grp {
0351 fsl,pins = <
0352 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
0353 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
0354 >;
0355 };
0356
0357 pinctrl_uart3: uart3grp {
0358 fsl,pins = <
0359 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
0360 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
0361 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
0362 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
0363 >;
0364 };
0365
0366 pinctrl_uart4: uart4grp {
0367 fsl,pins = <
0368 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
0369 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
0370 >;
0371 };
0372
0373 pinctrl_usdhc2: usdhc2grp {
0374 fsl,pins = <
0375 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090
0376 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0
0377 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0
0378 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0
0379 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0
0380 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0
0381 >;
0382 };
0383
0384 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
0385 fsl,pins = <
0386 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
0387 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
0388 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4
0389 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4
0390 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4
0391 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4
0392 >;
0393 };
0394
0395 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
0396 fsl,pins = <
0397 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
0398 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6
0399 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6
0400 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6
0401 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6
0402 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6
0403 >;
0404 };
0405
0406 pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
0407 fsl,pins = <
0408 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
0409 >;
0410 };
0411
0412 pinctrl_wdog: wdoggrp {
0413 fsl,pins = <
0414 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046
0415 >;
0416 };
0417
0418 pinctrl_wlan: wlangrp {
0419 fsl,pins = <
0420 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
0421 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
0422 MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
0423 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */
0424 >;
0425 };
0426 };
